ASIC RTL/SoC Design Engineer
Fremont, CA · On-site
Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...
Fremont, CA · On-site
Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...
Fremont, CA · On-site
Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...
As a Senior ASIC Design Engineer, you will own the complete RTL design lifecycle from micro-architecture specification through production silicon, working on complex IP design. THE PERSON: The ideal ...
As a Senior ASIC Design Engineer, you will own the complete RTL design lifecycle from micro-architecture specification through production silicon, working on complex IP design. THE PERSON: The ideal ...
RTL Design Engineer Building AI chips that are hard-coded for individual model architectures. RTL ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
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RTL Design Engineer Building AI chips that are hard-coded for individual model architectures. RTL ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
Develop RTL using SystemVerilog and perform synthesis.Verification: Engage with simulation-based ... Engineering, or a related field.Experience: 3+ years of proven experience in ASIC design, including ...
Develop RTL using SystemVerilog and perform synthesis.Verification: Engage with simulation-based ... Engineering, or a related field.Experience: 3+ years of proven experience in ASIC design, including ...
ASIC Design Engineer Responsibilities: * Define and bring up FPGA platforms for pre-silicon ... Map ASIC RTL to FGPA while minimizing code base differences * Create and execute test plans for ...
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ASIC Design Engineer Responsibilities: * Define and bring up FPGA platforms for pre-silicon ... Map ASIC RTL to FGPA while minimizing code base differences * Create and execute test plans for ...
Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ... Engineering, or a related field. Experience: 3+ years of proven experience in ASIC design ...
Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ... Engineering, or a related field. Experience: 3+ years of proven experience in ASIC design ...
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Develop RTL using SystemVerilog and perform synthesis.Verification: Engage with simulation-based ...
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Develop RTL using SystemVerilog and perform synthesis.Verification: Engage with simulation-based ...
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ...
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ...
Sunnyvale, CA · On-site +1
$204K - $306K/yr
... RTL, reviewing detailed design implementations, and guiding engineers through complex debug and ... Leading and managing a team of ASIC digital design engineers, providing daytoday technical guidance ...
Sunnyvale, CA · On-site +1
$204K - $306K/yr
... RTL, reviewing detailed design implementations, and guiding engineers through complex debug and ... Leading and managing a team of ASIC digital design engineers, providing daytoday technical guidance ...
ASIC Design Engineer( Remote) MUST HAVE: AEROSPACE , DEEP UNDERSTANDING ASIC, DO254, DIGITAL ... Write RTL (Register Transfer Level) code in Verilog or VHDL , and perform simulations using ...
ASIC Design Engineer( Remote) MUST HAVE: AEROSPACE , DEEP UNDERSTANDING ASIC, DO254, DIGITAL ... Write RTL (Register Transfer Level) code in Verilog or VHDL , and perform simulations using ...
San Jose, CA · On-site
Design Engineer We are an established semiconductor company focused on storage related product ... What You Need for this Position - OVM / UVM - SOC - ASIC - RTL - Logic Design - Front End - Digital ...
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San Jose, CA · On-site
Design Engineer We are an established semiconductor company focused on storage related product ... What You Need for this Position - OVM / UVM - SOC - ASIC - RTL - Logic Design - Front End - Digital ...
Boise, ID · On-site
$129.40K/yr
Job Summary Micron Technology seeks an RTL Build Engineer to develop DRAM digital blocks from ... Strong understanding of ASIC front-end flows including RTL design, synthesis, and static timing ...
Boise, ID · On-site
$129.40K/yr
Job Summary Micron Technology seeks an RTL Build Engineer to develop DRAM digital blocks from ... Strong understanding of ASIC front-end flows including RTL design, synthesis, and static timing ...
Cupertino, CA · On-site
$2K/mo
RTL Design Engineer As an RTL Engineer at Etched, you will be critical in ensuring that our AI ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
Cupertino, CA · On-site
$2K/mo
RTL Design Engineer As an RTL Engineer at Etched, you will be critical in ensuring that our AI ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
Cupertino, CA · On-site
$2K/mo
RTL Design Engineer As an RTL Engineer at Etched, you will be critical in ensuring that our AI ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
Cupertino, CA · On-site
$2K/mo
RTL Design Engineer As an RTL Engineer at Etched, you will be critical in ensuring that our AI ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
ASIC / VLSI ENGINEERS - RTL / STA / PD / DV (Senior Level) We are hiring 4 experienced ASIC / VLSI ... RTL Engineer (Networking / Ethernet) * STA Engineer * Physical Design Engineer * Design ...
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ASIC / VLSI ENGINEERS - RTL / STA / PD / DV (Senior Level) We are hiring 4 experienced ASIC / VLSI ... RTL Engineer (Networking / Ethernet) * STA Engineer * Physical Design Engineer * Design ...
Boise, ID · On-site
$129.40K/yr
Job Summary Micron Technology seeks an RTL Build Engineer to develop DRAM digital blocks from ... Strong understanding of ASIC front-end flows including RTL design, synthesis, and static timing ...
Boise, ID · On-site
$129.40K/yr
Job Summary Micron Technology seeks an RTL Build Engineer to develop DRAM digital blocks from ... Strong understanding of ASIC front-end flows including RTL design, synthesis, and static timing ...
Sunnyvale, CA · On-site
$159.60K/yr
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. * 2 years of experience in ASIC RTL design, with a focus on ...
Sunnyvale, CA · On-site
$159.60K/yr
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. * 2 years of experience in ASIC RTL design, with a focus on ...
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. * 4 years of experience in ASIC RTL design, with a focus on ...
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. * 4 years of experience in ASIC RTL design, with a focus on ...
Austin, TX · On-site
$138K/yr
Define and develop ASIC RTL design and verification at both chip level and block level ... Conduct design reviews and provide technical guidance to junior engineers. * Work closely with ...
Austin, TX · On-site
$138K/yr
Define and develop ASIC RTL design and verification at both chip level and block level ... Conduct design reviews and provide technical guidance to junior engineers. * Work closely with ...
Austin, TX · On-site
$181K - $271K/yr
... 2026 Job Category Engineering Job Subcategory ASIC Digital Design Hire Type Employee Remote ... Defining and developing ASIC RTL design and verification at both chip and block levels. * Creating ...
Austin, TX · On-site
$181K - $271K/yr
... 2026 Job Category Engineering Job Subcategory ASIC Digital Design Hire Type Employee Remote ... Defining and developing ASIC RTL design and verification at both chip and block levels. * Creating ...
$94K - $103.8K
16% of jobs
$103.8K - $113.6K
3% of jobs
$113.6K - $123.5K
4% of jobs
$126.3K is the 25th percentile. Wages below this are outliers.
$123.5K - $133.3K
6% of jobs
The median wage is $139.4K / yr.
$133.3K - $143.1K
33% of jobs
$143.1K - $152.9K
3% of jobs
$152.9K - $162.7K
2% of jobs
$169.2K is the 75th percentile. Wages above this are outliers.
$162.7K - $172.5K
12% of jobs
$172.5K - $182.4K
5% of jobs
$182.4K - $192.2K
4% of jobs
$192.2K - $202K
12% of jobs
$94K
$150.2K
$202K
| Aspect | Contractual Asic Rtl Design Engineer | Digital IC Design Engineer |
|---|---|---|
| Credentials | Bachelor's/Master's in Electrical Engineering or Computer Engineering | Bachelor's/Master's in Electrical Engineering or Computer Engineering |
| Work Environment | Contract-based, project-specific, often in semiconductor or tech companies | Full-time or contract, working on digital integrated circuit design |
| Industry Usage | Common in semiconductor, electronics, and tech firms for ASIC development | Used across semiconductor, consumer electronics, and communication industries |
Both roles require similar educational backgrounds and work in related environments, focusing on digital circuit design. The main difference is that Contractual Asic Rtl Design Engineers typically work on specific ASIC projects on a contractual basis, while Digital IC Design Engineers may have broader responsibilities in digital chip development, often in full-time roles.

Full-time
Medical, Retirement, PTO
Posted 21 days ago
TetraMem is a fast-growing well-funded startup company working on the next generation of computing platforms with unique ReRAM-based in-memory computing technologies. We are hiring in multiple positions from software to hardware.
We offer a very competitive compensation, commensurate with experience, and a full benefits package including medical, professional PTO, 401k, and other perks.
Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring robust and efficient designs.
Integrate and validate IP blocks within the larger system, ensuring seamless functionality and compatibility.
Thoroughly comprehend both internal and external requirements, conducting Power, Performance, and Area (PPA) analysis to optimize design trade-offs.
Collaborate closely with the backend team, participating in RTL coding, implementation, and synthesis stages to ensure successful tapeout.
Develop and maintain reusable internal intellectual properties (IPs) tailored for AI and/or in-memory computing applications.
Provide crucial support for Post-Si testing and validation, diagnosing and rectifying issues to ensure the overall functionality and quality of the product.
Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best practices to foster their professional growth.
Contribute to design reviews and cross-functional discussions, offering insights and recommendations to enhance product performance and reliability.
Stay up-to-date with industry trends and advancements in RTL design methodologies, integrating innovative techniques to improve product quality and efficiency.
Collaborate with cross-functional teams, including software, architecture, and verification teams, to achieve cohesive and successful product development and delivery.
MS with 5+ years of experience or PhD in Electrical Engineering with emphasis on RTL/SoC/digital design
Experience with Verilog and system Verilog
Experience with VCS, Verdi or other industry standard tools
Experience with pre-layout simulation and post-layout simulation
Understanding of the design flow. Ability to work with the backend team
Familiarity with AMBA APB AXI Protocol
Familiarity with RISC/Arm or other core architectures
Ability to create innovative architecture and solutions to customer requirements
Ability to work in startup environment and work both independently and as a team player, with the ability to provide technical leadership to other members of the engineering team.
Experience in one or more of the following areas considered a strong plus:
FPGA/ASIC design of image processing systems
Working knowledge of SoC architecture such as CPU, GPU or accelerators
Familiarity with: UVM, place-and-route, STA, EM/IR/Power
All your information will be kept confidential according to EEO guidelines.
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Computer and peripheral equipment manufacturing
11 - 50 Employees
Fremont, CA, US
2018