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Contractual Asic Rtl Design Engineer Jobs (NOW HIRING)

Apple

ASIC Design and Integration Engineer

Beaverton, OR · On-site

Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ...

TetraMem Inc

ASIC RTL/SoC Design Engineer

San Jose, CA · On-site

$110K - $300K/yr

Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...

Google

TPU RTL Design Engineer

Sunnyvale, CA · On-site

$159K/yr

... in ASIC RTL design, with a focus on clocking, reset, or timing-critical RTL development ... Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not ...

Etech Hi

ASIC / VLSI Engineers

Milpitas, CA

ASIC / VLSI ENGINEERS - RTL / STA / PD / DV (Senior Level) We are hiring 4 experienced ASIC / VLSI ... RTL Engineer (Networking / Ethernet) * STA Engineer * Physical Design Engineer * Design ...

Etched

RTL Design Engineer

Cupertino, CA · On-site

$2.0K/mo

RTL Design Engineer As an RTL Engineer at Etched, you will be critical in ensuring that our AI ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...

Etched

RTL Design Engineer

Cupertino, CA · On-site

$2.0K/mo

RTL Design Engineer As an RTL Engineer at Etched, you will be critical in ensuring that our AI ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...

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All JobsContractual Asic Rtl Design Engineer Jobs

Contractual Asic Rtl Design Engineer information

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$94K

$150.2K

$202K

How much do contractual asic rtl design engineer jobs pay per year?

As of Jul 10, 2026, the average yearly pay for contractual asic rtl design engineer in the United States is $150,195.00, according to ZipRecruiter salary data. Most workers in this role earn between $131,500.00 and $180,000.00 per year, depending on experience, location, and employer.

What is the difference between Contractual Asic Rtl Design Engineer vs Digital IC Design Engineer?

AspectContractual Asic Rtl Design EngineerDigital IC Design Engineer
CredentialsBachelor's/Master's in Electrical Engineering or Computer EngineeringBachelor's/Master's in Electrical Engineering or Computer Engineering
Work EnvironmentContract-based, project-specific, often in semiconductor or tech companiesFull-time or contract, working on digital integrated circuit design
Industry UsageCommon in semiconductor, electronics, and tech firms for ASIC developmentUsed across semiconductor, consumer electronics, and communication industries

Both roles require similar educational backgrounds and work in related environments, focusing on digital circuit design. The main difference is that Contractual Asic Rtl Design Engineers typically work on specific ASIC projects on a contractual basis, while Digital IC Design Engineers may have broader responsibilities in digital chip development, often in full-time roles.

More about Contractual Asic Rtl Design Engineer jobs
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Contractual Asic Rtl Design Engineer jobs near you
Infographic showing various Contractual Asic Rtl Design Engineer job openings in the United States as of July 2026, with employment types broken down into 33% Internship, and 67% Contract. Highlights an 67% In-person, and 33% Remote job distribution, with an average salary of $150,195 per year, or $72.2 per hour.
ASIC RTL/SoC Design Engineer

ASIC RTL/SoC Design Engineer

TetraMem - Accelerate The World

San Jose, CA • On-site

$110K - $300K/yr

Other

Re-posted 14 hours ago

Job description

Responsibilities:

  • Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring robust and efficient designs
  • Integrate and validate IP blocks within the larger system, ensuring seamless functionality and compatibility
  • Thoroughly comprehend both internal and external requirements, conducting Power, Performance, and Area (PPA) analysis to optimize design trade-offs
  • Collaborate closely with the backend team, participating in RTL coding, implementation, and synthesis stages to ensure successful tapeout
  • Develop and maintain reusable internal intellectual properties (IPs) tailored for AI and/or in-memory computing applications
  • Provide crucial support for Post-Si testing and validation, diagnosing and rectifying issues to ensure the overall functionality and quality of the product
  • Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best practices to foster their professional growth
  • Contribute to design reviews and cross-functional discussions, offering insights and recommendations to enhance product performance and reliability
  • Stay up-to-date with industry trends and advancements in RTL design methodologies, integrating innovative techniques to improve product quality and efficiency
  • Collaborate with cross-functional teams, including software, architecture, and verification teams, to achieve cohesive and successful product development and delivery


Requirements:

  • MS with 5+ years of experience or PhD in Electrical Engineering with emphasis on RTL/SoC/digital design
  • Experience with Verilog and system Verilog
  • Experience with VCS, Verdi or other industry standard tools
  • Experience with pre-layout simulation and post-layout simulation
  • Understanding of the design flow. Ability to work with the backend team
  • Familiarity with AMBA APB AXI Protocol
  • Familiarity with RISC/Arm or other core architectures
  • Ability to create innovative architecture and solutions to customer requirements
  • Ability to work in startup environment and work both independently and as a team player, with the ability to provide technical leadership to other members of the engineering team.


Experience in one or more of the following areas considered a strong plus:

  • FPGA/ASIC design of image processing systems
  • Working knowledge of SoC architecture such as CPU, GPU or accelerators
  • Familiarity with: UVM, place-and-route, STA, EM/IR/Power

Salary Range: $110,000 - $300,000 / year

TetraMem celebrates diversity and is committed to creating an inclusive environment for all employees. We are proud to be an Equal Opportunity Employer and welcome applicants from all backgrounds. Qualified candidates will receive consideration for employment without regard to race, color, religion, creed, sex, gender identity or expression, sexual orientation, national origin, ancestry, age, marital status, medical condition, disability, genetic information, military or veteran status, or any other characteristic protected by applicable federal, state, or local law.
TetraMem is committed to providing reasonable accommodations to qualified applicants with disabilities throughout the recruitment process. Applicants requiring accommodation may contact Human Resources for assistance.
To ensure a fair, consistent, and efficient hiring process, all candidates must apply through TetraMems official ClearCompany Applicant Tracking System (ATS). Applications submitted through the ATS allow our hiring team to evaluate candidates using a standardized process and ensure timely communication throughout the recruitment process. To promote equal consideration for all applicants, applications submitted outside of the ClearCompany ATS, including direct emails, LinkedIn messages, or unsolicited submissions to employees, may not be reviewed or considered.
We encourage all interested candidates to apply through the official TetraMem Careers page.

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