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Temporary Asic Rtl Design Engineer Jobs (NOW HIRING)

Qualcomm

Processor ASIC RTL Design Engineer

San Diego, CA · On-site

$127K - $190K/yr

Engineering Group, Engineering Group > DSP Architecture and Design General Summary: A variety of ... This position involves in-depth understanding of the ASIC design flow from RTL to GDS2 and the ...

CYNET SYSTEMS

ASIC/RTL Design Engineer 2

San Jose, CA · On-site

$60 - $62/hr

Hands-on experience in industry ASIC design flow including RTL coding, debugging/verification, and supporting synthesis and timing closure. * Working knowledge of Client cores and other I/O standard ...

ServerLogic

Senior ASIC Design Engineer

Beaverton, OR · On-site

Sr/ ASIC Design Engineer (5+ Years of Experience) DESCRIPTION OF POSITION/DUTIES - * Architect a ... Run LINT and CDC checks on the RTL code and fix accordingly. * Assist with synthesis and FPGA ...

TetraMem INC

ASIC RTL/SoC Design Engineer

Fremont, CA · On-site

Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...

Normal Computing

RTL Design Engineer

New York, NY · On-site

$205K - $285K/yr

The Role As an RTL Design Engineer at Normal, you will design and verify the digital logic at the ... This work sits at the intersection of classical ASIC design, novel computing architectures, and a ...

New

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Temporary Asic Rtl Design Engineer information

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$94K

$150.2K

$202K

How much do temporary asic rtl design engineer jobs pay per year?

As of Jul 10, 2026, the average yearly pay for temporary asic rtl design engineer in the United States is $150,195.00, according to ZipRecruiter salary data. Most workers in this role earn between $131,500.00 and $180,000.00 per year, depending on experience, location, and employer.

What is the difference between Temporary Asic Rtl Design Engineer vs Temporary FPGA Design Engineer?

AspectTemporary Asic Rtl Design EngineerTemporary FPGA Design Engineer
Primary FocusDesigning RTL code for ASIC chipsDesigning FPGA logic and configurations
Skills & CertificationsVerilog/VHDL, ASIC design flow, simulation toolsVerilog/VHDL, FPGA development tools, synthesis
Work EnvironmentSemiconductor companies, ASIC design teamsFPGA development labs, prototyping environments
Industry UsageUsed in high-volume chip manufacturingUsed for prototyping, testing, and low-volume products

Both roles involve RTL design using Verilog or VHDL, but the Temporary Asic Rtl Design Engineer focuses on ASIC chip development, while the Temporary FPGA Design Engineer specializes in FPGA-based prototyping and testing. The choice depends on whether the project aims for mass production or flexible, rapid development.

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Temporary Asic Rtl Design Engineer jobs near you

RTL Engineer Networking ASIC Saratoga, CA Full-Time

VortexLink

Saratoga, CA • On-site

Other

Re-posted 11 days ago

Job description

RTL Engineer – Networking ASIC

Saratoga, CA
Full-Time

Join an innovative hardware company building next-generation Networking ASICs that power large-scale AI training and inference.

We are seeking experienced RTL Engineers to architect and implement high-performance networking chips focused on low latency, QoS, and scalability.

Responsibilities

  • Design packet buffering, queuing, and scheduling microarchitecture

  • Implement high-speed networking ASIC RTL (SystemVerilog/Verilog)

  • Optimize pipelined architectures for performance and latency

  • Support Ethernet, IP protocols, and high-speed interconnects (e.g., UCIe)

  • Collaborate with verification teams for testing and validation

Qualifications

  • BE/ME with 8–15 years of ASIC RTL design experience

  • Strong expertise in SystemVerilog & Verilog

  • Experience with scheduling, arbitration & QoS mechanisms

  • Solid understanding of ASIC design flow (simulation, synthesis, timing)

  • Background in Ethernet and IP networking protocols

If you’re passionate about building high-speed networking silicon for AI infrastructure, apply today.

Apply