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Temporary Asic Rtl Design Engineer Jobs (NOW HIRING)

Infoyogi LLC

ASIC/RTL Design Engineer

San Jose, CA

ASIC/RTL Design Engineer Location: San Jose, CA Duration : 12 months plus JOB DUTIES: The work will expose the designer to a number of IP including ARM cores, Ethernet, DDR, DMA, PCIE, SATA ...

VIVA USA INC

ASIC RTL Design Engineer

San Jose, CA · On-site

Our RTL Design Engineers are expected contribute in all aspects of SoC design including: Chip ... SoC Architecture; knowledge and hand-on experience from industry ASIC design flow including RTL ...

Qualcomm

Processor ASIC RTL Design Engineer

San Diego, CA · On-site

$127K - $190K/yr

Engineering Group, Engineering Group > DSP Architecture and Design General Summary: A variety of ... This position involves in-depth understanding of the ASIC design flow from RTL to GDS2 and the ...

CYNET SYSTEMS

ASIC/RTL Design Engineer 2

San Jose, CA · On-site

$60 - $62/hr

Hands-on experience in industry ASIC design flow including RTL coding, debugging/verification, and supporting synthesis and timing closure. * Working knowledge of Client cores and other I/O standard ...

Dexian DISYS

ASIC / SoC RTL Design Engineer

San Jose, CA

$60 - $62.50/hr

SoC RTL Design Engineer San Jose, CA: 100% Onsite 6 + Months $60-$62.50/HR Role: Lead advanced CMOS ... ASIC design flow experience Expert RTL coding/debugging Dexian stands at the forefront of Talent ...

Dexian

ASIC / SoC RTL Design Engineer

Campbell, CA · On-site

$60 - $62.50/hr

SoC RTL Design Engineer San Jose, CA: 100% Onsite 6 + Months $60-$62.50/HR Role: Lead advanced CMOS ... ASIC design flow experience Expert RTL coding/debugging Dexian stands at the forefront of Talent ...

Skywaves MP LLC

Senior RTL Design Engineer

Austin, TX

... ASIC/SoC Digital Design and RTL development. · Minimum 5+ years of hands-on experience in Verilog RTL design and development. · Strong understanding of digital design fundamentals, RTL design ...

New

ServerLogic

Senior ASIC Design Engineer

Beaverton, OR · On-site

Sr/ ASIC Design Engineer (5+ Years of Experience) DESCRIPTION OF POSITION/DUTIES - * Architect a ... Run LINT and CDC checks on the RTL code and fix accordingly. * Assist with synthesis and FPGA ...

TetraMem INC

ASIC RTL/SoC Design Engineer

Fremont, CA · On-site

Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...

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All JobsTemporary Asic Rtl Design Engineer Jobs

Temporary Asic Rtl Design Engineer information

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$94K

$150.2K

$202K

How much do temporary asic rtl design engineer jobs pay per year?

As of Jun 19, 2026, the average yearly pay for temporary asic rtl design engineer in the United States is $150,195.00, according to ZipRecruiter salary data. Most workers in this role earn between $131,500.00 and $180,000.00 per year, depending on experience, location, and employer.

What is the difference between Temporary Asic Rtl Design Engineer vs Temporary FPGA Design Engineer?

AspectTemporary Asic Rtl Design EngineerTemporary FPGA Design Engineer
Primary FocusDesigning RTL code for ASIC chipsDesigning FPGA logic and configurations
Skills & CertificationsVerilog/VHDL, ASIC design flow, simulation toolsVerilog/VHDL, FPGA development tools, synthesis
Work EnvironmentSemiconductor companies, ASIC design teamsFPGA development labs, prototyping environments
Industry UsageUsed in high-volume chip manufacturingUsed for prototyping, testing, and low-volume products

Both roles involve RTL design using Verilog or VHDL, but the Temporary Asic Rtl Design Engineer focuses on ASIC chip development, while the Temporary FPGA Design Engineer specializes in FPGA-based prototyping and testing. The choice depends on whether the project aims for mass production or flexible, rapid development.

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Temporary Asic Rtl Design Engineer jobs near you
Infographic showing various Temporary Asic Rtl Design Engineer job openings in the United States as of June 2026, with employment types broken down into 9% Locum Tenens, 9% Full Time, 27% Temporary, and 55% Contract. Highlights an 87% Physical, 5% Hybrid, and 8% Remote job distribution, with an average salary of $150,195 per year, or $72.2 per hour.
ASIC/RTL Design Engineer

ASIC/RTL Design Engineer

Infoyogi LLC

San Jose, CA

Other

Posted 17 days ago

Job description

ASIC/RTL Design Engineer

Location: San Jose, CA

Duration : 12 months plus

JOB DUTIES:

The work will expose the designer to a number of IP including ARM cores, Ethernet, DDR, DMA, PCIE, SATA

Successful candidates will be responsible for leading, and participating in, the design of leading edge SoCs in advanced digital CMOS processes. Our RTL Design Engineers are expected contribute in all aspects of SoC design including: Chip definition, Architecture development and modeling, Development of micro-architectural specifications, Conversion of micro-architectural specifications to logic implementation, Verification, emulation, debug, synthesis, and timing closure, Interfacing with physical execution, software, and silicon bring-up teams.

EXPERIENCE AND EDUCATION:

SoC Architecture; knowledge and hand-on experience from industry ASIC design flow including RTL coding, debugging/verification, and supporting synthesis and timing closure. Working knowledge of ARM cores and other I/O standard interfaces. An ideal candidate would also exhibit: Strong communication and documentation skills, Good organizational, time management and multitasking skills, Strong initiative and discipline to follow-through, Technical leadership

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