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Temporary Asic Rtl Design Engineer Jobs in Virginia

3B Staffing LLC

FPGA/ASIC Design Engineer

Reston, VA · On-site

$128K - $176.30K/yr

Technicall/Professional Reporting to the Manager, Engineering (ASIC/FPGA), the Design Engineer will ... RTL)) and RTL quality (RDC, CDC, Formal, Lint) Generate test plans Perform module level ...

Lynk

Senior FPGA Design Engineer

Chantilly, VA · On-site

As a Senior FPGA Engineer, you will support the development of custom radio platforms for the ... Design high-speed FPGA RTL designs for satellite communication systems * Understand the hardware ...

Leidos

FPGA Firmware Design Engineer

Arlington, VA

... engineers, scientists, etc) to design, develop, simulate, and integrate challenging DSP FPGA ... RTL and incorporate client feedback into firmware revisions. This role will also support ...

Leidos

FPGA Firmware Design Engineer

Arlington, VA · On-site

... engineers, scientists, etc) to design, develop, simulate, and integrate challenging DSP FPGA ... RTL and incorporate client feedback into firmware revisions. This role will also support ...

Leidos

FPGA Firmware Design Engineer

Arlington, VA

$87.10K - $157.45K/yr

... engineers, scientists, etc) to design, develop, simulate, and integrate challenging DSP FPGA ... RTL and incorporate client feedback into firmware revisions. This role will also support ...

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Temporary Asic Rtl Design Engineer information

What is the difference between Temporary Asic Rtl Design Engineer vs Temporary FPGA Design Engineer?

AspectTemporary Asic Rtl Design EngineerTemporary FPGA Design Engineer
Primary FocusDesigning RTL code for ASIC chipsDesigning FPGA logic and configurations
Skills & CertificationsVerilog/VHDL, ASIC design flow, simulation toolsVerilog/VHDL, FPGA development tools, synthesis
Work EnvironmentSemiconductor companies, ASIC design teamsFPGA development labs, prototyping environments
Industry UsageUsed in high-volume chip manufacturingUsed for prototyping, testing, and low-volume products

Both roles involve RTL design using Verilog or VHDL, but the Temporary Asic Rtl Design Engineer focuses on ASIC chip development, while the Temporary FPGA Design Engineer specializes in FPGA-based prototyping and testing. The choice depends on whether the project aims for mass production or flexible, rapid development.

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Temporary Asic Rtl Design Engineer jobs near you
FPGA/ASIC Design Engineer

FPGA/ASIC Design Engineer

3B Staffing LLC

Reston, VA • On-site

$128K - $176.30K/yr

Full-time

This job post has expired 1 day ago. Applications are no longer accepted.

Job description

Job Category:
Technicall/Professional
Job Description:
Reporting to the Manager, Engineering (ASIC/FPGA), the Design Engineer will be part of the key ASIC/FPGA design team, responsible for the delivery of FPGA/ASICs for high-speed crypto applications. S/he will architect, implement high speed crypto architectures, on ASICs/Xilinx Zynq/MPSOC class FPGAs, with hands on design/debug with Ethernet, TCP/IP protocols.
L3Harris has state-of-the-art EDA flows/methodologies including Synopsys DC/Primetime/Synplify, Xilinx/Intel/Microchip EDA with HLS, Mentor EDA Family suite : Questa, VIPs, UVM framework, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), Questa Lint, and Catapult (HLS).
This is a key, high impact role in the organization to ensure robust quality and delivery of communication products for National Security.
Skills/Experience:
Bachelors Degree in Electrical Engineering or equivalent degree, and minimum 4 years of prior relevant experience (or Masters Degree plus 2 years of prior relevant experience) developing, implementing, and verification of high-performance communications/networking ASIC/FPGA products.
Possess an active SECRET Clearance
Experience mapping algorithms and standards (Ethernet, TCP/IP, AXI) to hardware and architecture/system design tradeoffs.
Proficient in VHDL design process and FPGA flow
Knowledge of Ethernet, TCP/IP protocols
Strong logic/board debug, and analytical skills.
Excellent written, verbal, and presentation skills.
A PLUS for prior experience with:
High Level Synthesis (HLS) with Vivado,
Embedded SW C++ (OOP) and System Verilog Assertions (SVA)
Knowledge of high-speed protocols (PCIe, TCP/IP, Ethernet)
VHDL Experience is required for all candidates to be considered.
  • Looking for mid-senior level folks
  • Proficient in VHDL >5 yrs, Xilinx FPGA design EDA- Vivado
  • Must have done hands on multiple complex designs arch/design/verification/Synthesis/STA
  • Big Plus
    • Working with Ethernet protocol (not just instantiating the IP) Is a big plus.
    • Mentor EDA CDC/Lint/AC/RDC

Required Skills:
Derive engineering specifications from system requirements and develop detailed architecture
Execute design (RTL AND/OR HLS (C++ to RTL)) and RTL quality (RDC, CDC, Formal, Lint)
Generate test plans
Perform module level verification, synthesis/STA, Lab debug, SW driven validation on Linux based SOC evaluation boards
Silicon/FPGA bring up, characterization and production ramp/support/collateral
Desired Skills:
Prior experience in Aerospace / Defense
Experience in C++ (OOP)
Experience in Xilinx MPSOC design with writing/debugging with SDKs, BSPs on bare metal/PetaLinux OS.
Experience with High level synthesis (Xilinx Vivado HLS, AND/OR Mentor Calypto).
Experience with Universal Verification Mythology (UVM)
Experience with project leadership and EVM
Degree Requirements:
Bachelors Degree in Electrical Engineering or equivalent degree, and minimum 4 years of prior relevant experience (or Masters Degree plus 2 years of prior relevant experience) developing, implementing, and verification of high-performance communications/networking ASIC/FPGA products.

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