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Locum Asic Rtl Design Engineer Jobs in Virginia (NOW HIRING)

Fractile

Physical Design Engineer

Bristol, VA · On-site

$80 - $120/hr

Support the physical implementation of ASIC/SoC designs, including floor planning, placement, clock ... Work closely with RTL and architecture teams to support design feasibility, constraints, and ...

Fractile

Lead Physical Design Engineer

Bristol, VA · On-site

$120 - $180/hr

Key Responsibilities * Drive the physical implementation of ASIC/SoC designs, including ... Work closely with RTL and architecture teams to drive design feasibility, constraints, and physical ...

Peraton

Digital Design SME

Mclean, VA · On-site

$176K - $282K/yr

Application Specific Integrated Circuit (ASIC) design & fabrication, microprocessor design ... A Bachelor's Degree in Electrical Engineering, Computer Science, or any relevant technical field ...

Peraton

Digital Design SME

Mclean, VA · On-site

$176K - $282K/yr

Application Specific Integrated Circuit (ASIC) design & fabrication, microprocessor design ... A Bachelor's Degree in Electrical Engineering, Computer Science, or any relevant technical field ...

Peraton

Digital Design SME

Mclean, VA

$176K - $282K/yr

Application Specific Integrated Circuit (ASIC) design & fabrication, microprocessor design ... A Bachelor's Degree in Electrical Engineering, Computer Science, or any relevant technical field ...

Trident Systems Inc.

Senior FPGA Engineer

Fairfax, VA · On-site

$97 - $181/hr

Senior FPGA Engineer Requisition ID: 1806 Position Location: Fairfax, VA Position Reports To ... The ideal candidate brings deep expertise in RTL design, timing closure, simulation, and system ...

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Locum Asic Rtl Design Engineer information

What is the difference between Locum Asic Rtl Design Engineer vs Contract Asic Rtl Design Engineer?

AspectLocum Asic Rtl Design EngineerContract Asic Rtl Design Engineer
CredentialsTypically requires relevant engineering degrees and RTL design experienceSimilar credentials, often with specific RTL design certifications
Work EnvironmentTemporary, short-term assignments often in multiple locationsProject-based roles, usually in a fixed location or remote
Employer UsageUsed by agencies or companies needing immediate, short-term expertiseEngaged by companies or staffing agencies for project-specific work

Both roles involve RTL design skills for ASIC development, but a Locum Asic Rtl Design Engineer typically fills short-term, temporary positions, often through staffing agencies, while a Contract Asic Rtl Design Engineer is engaged for specific projects with defined durations. The main difference lies in the nature and duration of employment, but both require similar technical credentials and work environments.

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Locum Asic Rtl Design Engineer jobs near you

Physical Design Engineer

Fractile

Bristol, VA • On-site

$80 - $120/hr

Other

Posted 13 days ago

Job description

Fractile’s mission is to enable a new chapter in the AI revolution. We’re pioneering AI innovation where hardware and software join to create something extraordinary, unlocking the power of the world’s largest language models with speed increases of x100. Our team is rapidly expanding, and we're searching for visionary engineers, scientists, and thinkers who share our passion for pushing boundaries and redefining what's possible. If you're ready to join a dynamic group of innovators shaping AI's future, we want to hear from you!

We are seeking a Physical Design Engineer to contribute to our next‑generation chip designs. As a Physical Design Engineer, you will support the implementation of complex IC physical designs, from synthesis to sign‑off. You will collaborate with cross‑functional teams, including logic design, verification, and process technology, to optimise performance, power, and area (PPA) while ensuring design integrity and manufacturability.

Key Responsibilities:
  • Support the physical implementation of ASIC/SoC designs, including floor planning, placement, clock tree synthesis (CTS), routing, and sign‑off.
  • Work on synthesis, timing analysis (STA), and optimisation to achieve strong PPA metrics.
  • Assist in power planning and analysis, addressing IR drop, electromigration, and related effects.
  • Ensure design rule check (DRC), layout vs. schematic (LVS), and other physical verification compliance.
  • Collaborate with DFT engineers to integrate design‑for‑test (DFT) structures into the physical implementation.
  • Develop flows in EDA tools such as Cadence Innovus, Synopsys Fusion Compiler, Mentor Graphics Calibre, and others.
  • Work closely with RTL and architecture teams to support design feasibility, constraints, and physical‑aware RTL design.
  • Work with advanced AI tools and models to improve productivity, analysis, and design quality.
Preferred Qualifications:
  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
  • 0–5 years of experience in physical design for advanced technology nodes (e.g., 7nm, 5nm, or below), including internships.
  • Familiarity with EDA tools for place & route, STA, and sign‑off.
  • Basic understanding of CMOS technology, semiconductor physics, and process limitations.
  • Exposure to timing closure, signal integrity, IR drop analysis, and formal verification.
  • Proficiency in scripting languages like TCL, Perl, or Python for automation is a plus.
  • Excellent problem‑solving skills, communication, and teamwork in a collaborative design environment.
  • Interest in working with advanced AI tools and models as part of the design workflow.
  • Experience or coursework in high‑performance computing (HPC), AI accelerators, or networking chips is a plus.
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