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Junior Rtl Design Engineer Jobs in Virginia (NOW HIRING)

Mechanical Design Engineer

Henrico, VA · On-site

$69K - $93K/yr

Mechanical Design Engineer Location: Henrico, VA (Onsite) Job Summary Seeking a Mechanical Design ... Thanks & Regards, Mahalakshmi Junior Recruiter Intellectt Inc mahalakshmi.n@intellectt.com Direct ...

Senior FPGA Engineer

Fairfax, VA · On-site

$97K - $181K/yr

The ideal candidate brings deep expertise in RTL design, timing closure, simulation, and system ... Mentor junior engineers: provide training, guidance, and support as needed * Ability to support ...

Mechanical Design Engineer

Lyndhurst, VA · On-site

$73K - $99K/yr

Occasionally mentor junior engineers, sharing best practices, reviewing their work, and supporting their technical development. * Contribute to project coordination efforts, including design reviews ...

Mechanical Design Engineer

Lyndhurst, VA

$73K - $99K/yr

Occasionally mentor junior engineers, sharing best practices, reviewing their work, and supporting their technical development. * Contribute to project coordination efforts, including design reviews ...

... Mentor junior engineers and contribute to a culture of growth • Engage clients directly - define problems, develop solutions, sell the design Must-Have Qualifications • Active PE license ...

Collaborate with multidisciplinary teams including drainage, structures, traffic, and utilities. * Assist in mentoring or supporting junior engineers and interns on roadway design tools and DOT ...

Roadway Design Engineer

Sterling, VA · On-site

$85K - $115K/yr

Collaborate with multidisciplinary teams including drainage, structures, traffic, and utilities. * Assist in mentoring or supporting junior engineers and interns on roadway design tools and DOT ...

Staff Design Engineer

Staunton, VA · Hybrid

$109K - $188K/yr

This candidate will provide technical guidance to more junior team members. Come be a part of an ... Investigate engineering/manufacturing issues related to the assembly of the new product design and ...

... of RTL design for FPGAs in VHDL or Verilog, or System Verilog - knowledge of all 3 strongly ... C++ programming * Mapping data processing algorithms to FPGAs using Vitis HLS * Implementing AI/ML ...

... of RTL design for FPGAs in VHDL or Verilog, or System Verilog - knowledge of all 3 strongly ... C++ programming * Mapping data processing algorithms to FPGAs using Vitis HLS * Implementing AI/ML ...

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Junior Rtl Design Engineer information

See Virginia salary details

$33.2K

$71.2K

$108.6K

How much do junior rtl design engineer jobs pay per year?

As of Jul 8, 2026, the average yearly pay for junior rtl design engineer in Virginia is $71,184.00, according to ZipRecruiter salary data. Most workers in this role earn between $48,100.00 and $79,300.00 per year, depending on experience, location, and employer.

What engineers make $300,000 a year?

Senior engineers in specialized fields such as software engineering, petroleum engineering, and certain electrical or aerospace engineering roles can earn $300,000 or more annually, especially with extensive experience, advanced skills, and leadership responsibilities. High-level positions often require advanced degrees, certifications, and a strong track record of project management or technical expertise.

What is the salary of RTL design engineer?

The salary of a Junior RTL Design Engineer typically ranges from $70,000 to $100,000 annually, depending on experience, location, and company size. Entry-level positions may start lower, while experienced engineers with skills in Verilog, VHDL, and FPGA design can earn higher salaries.

What are the key skills and qualifications needed to thrive as a Junior RTL Design Engineer, and why are they important?

To thrive as a Junior RTL Design Engineer, a solid background in digital logic design, hardware description languages (such as Verilog or VHDL), and a relevant engineering degree are essential. Experience with simulation and synthesis tools (like ModelSim, Synopsys, or Xilinx Vivado) and a basic understanding of ASIC or FPGA flows are typically required. Strong analytical thinking, attention to detail, and effective teamwork skills help individuals excel in translating specifications into efficient hardware designs. These skills ensure accurate, reliable, and high-performance digital circuit development, which is crucial for meeting project goals and industry standards.

What engineers make $200,000 a year?

Senior engineers in fields such as software engineering, petroleum engineering, and certain specialized roles in finance or management can earn $200,000 or more annually. Achieving this level typically requires extensive experience, advanced skills, and often leadership responsibilities or specialized certifications.

What are Junior RTL Design Engineers?

Junior RTL Design Engineers are entry-level professionals who work on designing and verifying the Register Transfer Level (RTL) logic for digital integrated circuits. They typically use hardware description languages like Verilog or VHDL to describe and simulate the functionality of hardware blocks according to specifications. Their responsibilities often include coding, simulation, debugging, and collaborating with senior engineers to ensure the design meets performance and functional requirements. This role is crucial in the process of creating chips and digital systems used in various electronic devices.

What is the difference between Junior Rtl Design Engineer vs Digital Design Engineer?

AspectJunior Rtl Design EngineerDigital Design Engineer
Required CredentialsBachelor's in Electrical Engineering or related field; some certificationsBachelor's or higher in Electrical/Electronic Engineering; certifications vary
Work EnvironmentDesign teams in semiconductor or electronics companiesDesign and development teams in similar industries
Employer & Industry UsageCommonly employed in chip design, FPGA, ASIC developmentUsed in digital circuit and system design across industries

Both roles involve digital circuit design, but Junior Rtl Design Engineers focus more on RTL coding and verification, while Digital Design Engineers may handle broader digital system development. The roles often overlap in skills and work environment, with the main difference being scope and experience level.

What are some common challenges faced by Junior RTL Design Engineers when transitioning from academic projects to industry roles?

Junior RTL Design Engineers often find the transition from academic projects to industry roles challenging due to the increased complexity and scale of commercial designs. In industry, there is a strong emphasis on meeting strict timing, power, and area requirements, as well as adhering to rigorous verification and documentation standards. Collaboration with verification, physical design, and software teams is essential, and juniors may need to quickly adapt to using industry-standard EDA tools and workflows. Gaining proficiency in debugging and understanding legacy codebases are also typical hurdles. However, most teams provide mentorship and structured onboarding to help new engineers succeed.

What engineer makes $500,000 a year?

Senior engineers in specialized fields such as software engineering, data science, or executive engineering roles can earn $500,000 or more annually, especially with experience, advanced skills, and leadership responsibilities. High compensation often includes bonuses, stock options, or profit sharing, particularly in large tech companies or startups.
What job categories do people searching Junior Rtl Design Engineer jobs in Virginia look for? The top searched job categories for Junior Rtl Design Engineer jobs in Virginia are:
What cities in Virginia are hiring for Junior Rtl Design Engineer jobs? Cities in Virginia with the most Junior Rtl Design Engineer job openings:
FPGA/ASIC Design Engineer with Security Clearance

FPGA/ASIC Design Engineer with Security Clearance

Indotronix International Corp

Herndon, VA • On-site

$115/hr

Contractor

Re-posted 24 days ago


Job description

Job Title: FPGA/ASIC Design Engineer
Location: Herndon, VA
Duration: 12 Months
Pay: $115/hr on W2
Active Secret Clearance Reporting to the Manager, Engineering (ASIC/FPGA), the Senior Member of Engineering Staff (SMES) will be part of the key design team, responsible for the delivery of FPGAs for defense applications. S/he will architect, implement FPGA design, with hands on design/debug with primarily Ethernet, I2C, SPI, AXI protocols. L3Harris has state-of-the-art EDA flows/methodologies including Mentor EDA: Simulator Questa Prime, Verification IP (QVIPs), UVM framework, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), Questa Lint, Synopsys (DC/Primetime/Synplify), Xilinx/Intel/Microchip EDA (Vivado/Libero/Quartus). We are a learning organization and have the capability to target all FPGA vendors and have ASIC front end capability, with mature design processes. This is a high impact role in the organization to ensure robust quality and delivery of communication products for National Security. Essential Functions: Derive FPGA design specifications from system requirements
Develop detailed FPGA architecture for implementation
Implement design in RTL (VHDL) and perform module level simulations
Perform Synthesis, Place and Route (PAR) and Static Timing Analysis (STA)
Perform RTL quality using: Lint, Reset Domain Crossing (RDC), Clock Domain Crossing (CDC) , Static Formal EDA
Generate verification test plans and perform End to End Simulations
Support Board, FPGA bring up
Validate design through HW/SW integration test with test equipment
Support product collateral for NSA certification Qualifications: Bachelor of Science (BS) -Four year degree or Masters (MS) or PhD from an accredited course of study in engineering, engineering technology (chemistry, physics, mathematics, data science, or Electrical/Electronics/Computer Engineering/Computer Science)
3-5+ years’ experience designing FPGA products with VHDL
Experience with Xilinx FPGAs and Vivado
Experience with Revision control system
Experience with Earned Value Management (EVM)
Good written, verbal, and presentation skills
Active DoD Security Clearance Preferred Additional Skills: Experience with mapping algorithms to architecture
Experience in C++ (OOP)
Experience with any of protocols : Ethernet, TCP/IP, PCIe, NVMe, USB
Experience with Xilinx SoC design with SDKs and PetaLinux OS
Experience with High-Level Synthesis (HLS) with Vivado HLX or Mentor Catapult

Indotronix logo

About Indotronix

Sourced by ZipRecruiter

In 1986, Indotronix established itself in the staffing space. 22 years later, Avani entered the scene, offering consulting and technology development. Finally, in 2016, the two joined forces to begin delivering talent across all areas, from Staffing to Consulting to unique platform development.

Industry

Recruiting and staffing services

Company size

1,001 - 5,000 Employees

Headquarters location

Rochester, NY, US