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Junior Rtl Design Engineer Jobs in Virginia (NOW HIRING)

Work closely with RTL and architecture teams to drive design feasibility, constraints, and physical-aware RTL design. * Mentor junior engineers and contribute to building strong physical design ...

Digital Design Engineer

Lexington, VA · On-site

$150 - $200/hr

Experience with unit‑level and FPGA chip level verification of RTL * Experience with laboratory ... Experiencing developing, designing, and programmable logic for signal processing applications

Principal FPGA Engineer

Fairfax, VA · On-site

$150 - $200/hr

The ideal candidate brings deep expertise in RTL design, timing closure, simulation, and system ... Mentor junior engineers: provide training, guidance, and support as needed * Ability to support ...

Principal FPGA Engineer

Fairfax, VA · On-site

$116K - $216K/yr

The ideal candidate brings deep expertise in RTL design, timing closure, simulation, and system ... Mentor junior engineers: provide training, guidance, and support as needed * Ability to support ...

Mentor junior engineers and contribute to a culture of growth * Engage clients directly - define problems, develop solutions, sell the design Must-Have Qualifications * Active PE license (reciprocity ...

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Showing results 1-20

Junior Rtl Design Engineer information

See Virginia salary details

$33.2K

$71.2K

$108.6K

How much do junior rtl design engineer jobs pay per year?

As of Sep 8, 2026, the average yearly pay for junior rtl design engineer in Virginia is $71,184.00, according to ZipRecruiter salary data. Most workers in this role earn between $48,100.00 and $79,300.00 per year, depending on experience, location, and employer.

What is a junior RTL design engineer?

Junior RTL Design Engineers are entry-level professionals who work on designing and verifying the Register Transfer Level (RTL) logic for digital integrated circuits. They typically use hardware description languages like Verilog or VHDL to describe and simulate the functionality of hardware blocks according to specifications. Their responsibilities often include coding, simulation, debugging, and collaborating with senior engineers to ensure the design meets performance and functional requirements. This role is crucial in the process of creating chips and digital systems used in various electronic devices.

What are the key skills and qualifications needed to thrive as a junior RTL design engineer?

To thrive as a Junior RTL Design Engineer, a solid background in digital logic design, hardware description languages (such as Verilog or VHDL), and a relevant engineering degree are essential. Experience with simulation and synthesis tools (like ModelSim, Synopsys, or Xilinx Vivado) and a basic understanding of ASIC or FPGA flows are typically required. Strong analytical thinking, attention to detail, and effective teamwork skills help individuals excel in translating specifications into efficient hardware designs. These skills ensure accurate, reliable, and high-performance digital circuit development, which is crucial for meeting project goals and industry standards.

What are some common challenges faced by junior RTL design engineers when transitioning from academic projects to industry roles?

Junior RTL Design Engineers often find the transition from academic projects to industry roles challenging due to the increased complexity and scale of commercial designs. In industry, there is a strong emphasis on meeting strict timing, power, and area requirements, as well as adhering to rigorous verification and documentation standards. Collaboration with verification, physical design, and software teams is essential, and juniors may need to quickly adapt to using industry-standard EDA tools and workflows. Gaining proficiency in debugging and understanding legacy codebases are also typical hurdles. However, most teams provide mentorship and structured onboarding to help new engineers succeed.

What is the difference between Junior Rtl Design Engineer vs Digital Design Engineer?

AspectJunior Rtl Design EngineerDigital Design Engineer
Required CredentialsBachelor's in Electrical Engineering or related field; some certificationsBachelor's or higher in Electrical/Electronic Engineering; certifications vary
Work EnvironmentDesign teams in semiconductor or electronics companiesDesign and development teams in similar industries
Employer & Industry UsageCommonly employed in chip design, FPGA, ASIC developmentUsed in digital circuit and system design across industries

Both roles involve digital circuit design, but Junior Rtl Design Engineers focus more on RTL coding and verification, while Digital Design Engineers may handle broader digital system development. The roles often overlap in skills and work environment, with the main difference being scope and experience level.

What cities in Virginia are hiring for Junior Rtl Design Engineer jobs?

Cities in Virginia with the most Junior Rtl Design Engineer job openings:

Lead Physical Design Engineer

Fractile

Bristol, VA • On-site

$150 - $200/hr

Other

Re-posted 3 days ago


Key responsibilities

  • Drive the physical implementation of ASIC/SoC designs, including floorplanning, placement, clock tree synthesis, routing, and sign-off.

  • Lead or contribute to full-chip execution, block ownership, team leadership, or chip leadership, depending on project needs.

  • Collaborate with cross-functional teams to optimise performance, power, and area (PPA) while ensuring design integrity and manufacturability.


Job description

Fractile’s mission is to enable a new chapter in the AI revolution. We’re pioneering AI innovation where hardware and software join to create something extraordinary, unlocking the power of the world’s largest language models with speed increases of x100. Our team is rapidly expanding, and we're searching for visionary engineers, scientists, and thinkers who share our passion for pushing boundaries and redefining what's possible. If you're ready to join a dynamic group of innovators shaping AI's future, we want to hear from you!

We are seeking a highly skilled Lead Physical Design Engineer to contribute to our next-generation chip designs. As a Lead Physical Design Engineer, you will be responsible for the end-to-end implementation of complex IC physical designs, from synthesis to sign-off. In this role, you will take on leadership responsibilities across multiple dimensions, including full-chip ownership, leading a team of physical design engineers, and contributing to broader chip-level physical design leadership. You will collaborate with cross-functional teams, including logic design, verification, and process technology, to optimise performance, power, and area (PPA) while ensuring design integrity and manufacturability.

Key Responsibilities
  • Drive the physical implementation of ASIC/SoC designs, including floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off.
  • Lead or contribute to full-chip execution, block ownership, team leadership, or chip leadership, depending on project needs.
  • Work on synthesis, timing analysis (STA), and optimisation to achieve the best PPA metrics.
  • Own power planning and analysis, addressing IR drop, electromigration, and related effects.
  • Ensure design rule check (DRC), layout vs. schematic (LVS), and other physical verification compliance.
  • Collaborate with DFT engineers to integrate design-for-test (DFT) structures into the physical implementation.
  • Develop and improve flows in EDA tools such as Cadence Innovus, Synopsys Fusion Compiler, Mentor Graphics Calibre, and others.
  • Work closely with RTL and architecture teams to drive design feasibility, constraints, and physical-aware RTL design.
  • Mentor junior engineers and contribute to building strong physical design practices across the team.
  • Work with advanced AI tools and models to improve productivity, analysis, and design quality.
Preferred Qualifications
  • Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a related field.
  • 10+ years of experience in physical design for advanced technology nodes (e.g., 7nm, 5nm, or below).
  • Strong proficiency in EDA tools for place & route, STA, and sign-off.
  • Solid understanding of CMOS technology, semiconductor physics, and process limitations.
  • Expertise in timing closure, signal integrity, IR drop analysis, and formal verification.
  • Proficiency in scripting languages like TCL, Perl, or Python for automation.
  • Proven ability to take ownership of complex designs and drive them to completion.
  • Experience mentoring engineers and leading physical design efforts.
  • Excellent problem-solving skills, communication, and teamwork in a collaborative design environment.
  • Experience in high-performance computing (HPC), AI accelerators, or networking chips.
  • Experience or strong interest in leveraging advanced AI tools and models within engineering workflows.

Fractile is building silicon, systems and software which will redefine the frontier of AI: running the world’s most advanced models at radically higher speed and lower cost. We have an exceptional team across hardware and software capable of bringing about this change, and we are growing fast to meet demand and deliver our product at scale.

How we work
  • Ownership and execution: you will have full agency to drive your work forward
  • Rapid iteration: we all work directly with top leadership to move from idea to hardware on ambitious timelines
  • Full-stack engagement: hardware, software, silicon, and modelling teams all work closely together to create a product with generational impact
  • Optimistic and pragmatic: we possess the will to win, and to do the hard work to get us there
  • Team player mentality: the mission is bigger than any of us, and we have the curiosity and technical focus to see the best idea shipped, no matter who’s it is
About us
  • Founded in 2022, team of 90+ which is expanding rapidly
  • Modern, open offices in London and Bristol
  • Collaborative, problem-solving culture built on deep curiosity, entrepreneurial initiative and technical fluency
Export control and security clearance

Certain roles may involve working on technologies subject to export restrictions. Applicants may be required to undergo additional eligibility checks to ensure compliance with applicable law.

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