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Junior Rtl Design Engineer Jobs in Reston, VA (NOW HIRING)

Trident Systems LLC

Senior FPGA Engineer

Fairfax, VA · On-site

$97K - $181K/yr

The ideal candidate brings deep expertise in RTL design, timing closure, simulation, and system ... Mentor junior engineers: provide training, guidance, and support as needed * Ability to support ...

Alpha

Roadway Design Engineer

Baltimore, MD

$85K - $115K/yr

Collaborate with multidisciplinary teams including drainage, structures, traffic, and utilities. * Assist in mentoring or supporting junior engineers and interns on roadway design tools and DOT ...

Alpha Corporation

Roadway Design Engineer

Sterling, VA · On-site

$85K - $115K/yr

Collaborate with multidisciplinary teams including drainage, structures, traffic, and utilities. * Assist in mentoring or supporting junior engineers and interns on roadway design tools and DOT ...

Logos Technologies, Inc.

Engineer

Fairfax, VA

... of RTL design for FPGAs in VHDL or Verilog, or System Verilog - knowledge of all 3 strongly ... C++ programming * Mapping data processing algorithms to FPGAs using Vitis HLS * Implementing AI/ML ...

Logos Technologies, Inc.

Engineer

Fairfax, VA · On-site

... of RTL design for FPGAs in VHDL or Verilog, or System Verilog - knowledge of all 3 strongly ... C++ programming * Mapping data processing algorithms to FPGAs using Vitis HLS * Implementing AI/ML ...

Curtiss-Wright

Principal FPGA Engineer

Ashburn, VA

$144K - $192K/yr

You will also mentor junior engineers and provide technical guidance across projects. You will ... Strong understanding of FPGA design flow, including RTL design (System Verilog, Verilog, or VHDL ...

Curtiss-Wright

Principal FPGA Engineer

Ashburn, VA · On-site

$144K - $192K/yr

You will also mentor junior engineers and provide technical guidance across projects. You will ... Strong understanding of FPGA design flow, including RTL design (System Verilog, Verilog, or VHDL ...

Curtiss-Wright

Principal FPGA Engineer

Ashburn, VA

$144K - $192K/yr

You will also mentor junior engineers and provide technical guidance across projects. You will ... Strong understanding of FPGA design flow, including RTL design (System Verilog, Verilog, or VHDL ...

Curtisswright

Principal FPGA Engineer

Ashburn, VA · On-site

$144K - $192K/yr

You will also mentor junior engineers and provide technical guidance across projects. You will ... Strong understanding of FPGA design flow, including RTL design (System Verilog, Verilog, or VHDL ...

Logos Technologies, Inc.

Engineer

Fairfax, VA

... of RTL design for FPGAs in VHDL or Verilog, or System Verilog - knowledge of all 3 strongly ... C++ programming * Mapping data processing algorithms to FPGAs using Vitis HLS * Implementing AI/ML ...

Curtiss-Wright

Principal FPGA Engineer

Ashburn, VA · On-site

$144K - $192K/yr

You will also mentor junior engineers and provide technical guidance across projects. You will ... Strong understanding of FPGA design flow, including RTL design (System Verilog, Verilog, or VHDL ...

KBR

Senior Mechanical Design Engineer

Washington, DC · On-site

$150K - $190K/yr

Experience leading design efforts and mentoring junior engineers. Preferred Qualifications * Experience in electronics packaging, including thermal and structural considerations. * Familiarity with ...

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Junior Rtl Design Engineer information

See Reston, VA salary details

$34.9K

$74.7K

$113.9K

How much do junior rtl design engineer jobs pay per year?

As of Jul 8, 2026, the average yearly pay for junior rtl design engineer in Reston, VA is $74,697.00, according to ZipRecruiter salary data. Most workers in this role earn between $50,500.00 and $83,200.00 per year, depending on experience, location, and employer.

What engineers make $300,000 a year?

Senior engineers in specialized fields such as software engineering, petroleum engineering, and certain electrical or aerospace engineering roles can earn $300,000 or more annually, especially with extensive experience, advanced skills, and leadership responsibilities. High-level positions often require advanced degrees, certifications, and a strong track record of project management or technical expertise.

What is the salary of RTL design engineer?

The salary of a Junior RTL Design Engineer typically ranges from $70,000 to $100,000 annually, depending on experience, location, and company size. Entry-level positions may start lower, while experienced engineers with skills in Verilog, VHDL, and FPGA design can earn higher salaries.

What are the key skills and qualifications needed to thrive as a Junior RTL Design Engineer, and why are they important?

To thrive as a Junior RTL Design Engineer, a solid background in digital logic design, hardware description languages (such as Verilog or VHDL), and a relevant engineering degree are essential. Experience with simulation and synthesis tools (like ModelSim, Synopsys, or Xilinx Vivado) and a basic understanding of ASIC or FPGA flows are typically required. Strong analytical thinking, attention to detail, and effective teamwork skills help individuals excel in translating specifications into efficient hardware designs. These skills ensure accurate, reliable, and high-performance digital circuit development, which is crucial for meeting project goals and industry standards.

What engineers make $200,000 a year?

Senior engineers in fields such as software engineering, petroleum engineering, and certain specialized roles in finance or management can earn $200,000 or more annually. Achieving this level typically requires extensive experience, advanced skills, and often leadership responsibilities or specialized certifications.

What are Junior RTL Design Engineers?

Junior RTL Design Engineers are entry-level professionals who work on designing and verifying the Register Transfer Level (RTL) logic for digital integrated circuits. They typically use hardware description languages like Verilog or VHDL to describe and simulate the functionality of hardware blocks according to specifications. Their responsibilities often include coding, simulation, debugging, and collaborating with senior engineers to ensure the design meets performance and functional requirements. This role is crucial in the process of creating chips and digital systems used in various electronic devices.

What is the difference between Junior Rtl Design Engineer vs Digital Design Engineer?

AspectJunior Rtl Design EngineerDigital Design Engineer
Required CredentialsBachelor's in Electrical Engineering or related field; some certificationsBachelor's or higher in Electrical/Electronic Engineering; certifications vary
Work EnvironmentDesign teams in semiconductor or electronics companiesDesign and development teams in similar industries
Employer & Industry UsageCommonly employed in chip design, FPGA, ASIC developmentUsed in digital circuit and system design across industries

Both roles involve digital circuit design, but Junior Rtl Design Engineers focus more on RTL coding and verification, while Digital Design Engineers may handle broader digital system development. The roles often overlap in skills and work environment, with the main difference being scope and experience level.

What are some common challenges faced by Junior RTL Design Engineers when transitioning from academic projects to industry roles?

Junior RTL Design Engineers often find the transition from academic projects to industry roles challenging due to the increased complexity and scale of commercial designs. In industry, there is a strong emphasis on meeting strict timing, power, and area requirements, as well as adhering to rigorous verification and documentation standards. Collaboration with verification, physical design, and software teams is essential, and juniors may need to quickly adapt to using industry-standard EDA tools and workflows. Gaining proficiency in debugging and understanding legacy codebases are also typical hurdles. However, most teams provide mentorship and structured onboarding to help new engineers succeed.

What engineer makes $500,000 a year?

Senior engineers in specialized fields such as software engineering, data science, or executive engineering roles can earn $500,000 or more annually, especially with experience, advanced skills, and leadership responsibilities. High compensation often includes bonuses, stock options, or profit sharing, particularly in large tech companies or startups.
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Junior Rtl Design Engineer jobs near you
Programmable Logic Design Engineer

Programmable Logic Design Engineer

Viasat, Inc.

Germantown, MD

$193K - $290K/yr

Contractor

Re-posted 9 days ago

Viasat rating

4.2

Company rating: 4.2 out of 10

Based on 7 frontline employees who took The Breakroom Quiz

77th of 80 rated telecommunications companies

Job description

About us

One team. Global challenges. Infinite opportunities. At Viasat, we’re on a mission to deliver connections with the capacity to change the world. For more than 35 years, Viasat has helped shape how consumers, businesses, governments and militaries around the globe communicate. We’re looking for people who think big, act fearlessly, and create an inclusive environment that drives positive impact to join our team.


What you'll do

In this role you will help develop high speed signal processing algorithms and/or network protocols in FPGAs. The individual will be responsible for the full design phase starting from the requirements' phase to documentation, block diagrams, implementation of source code, simulation, place & route, testing in hardware, and integration.


The day-to-day
  • Collaborate with team members to jointly develop high-speed digital signal processing and waveform processing algorithms supporting satellite communications applications
  • Develop testbenches and help maintain and update system level verification environment
  • Synthesize Verilog and System Verilog for Xilinx/AMD FPGAs
  • Develop timing constraints, analyze timing results, and implement design changes required to close timing
  • Generate and collaborate on required design documents, development requirements, specifications and verification protocols
  • Responsible for owning and driving technical issues to resolution
  • Integrate and debugs design in the laboratory

What you'll need
  • Bachelor's Degree in Electrical Engineering, Computer Engineering or a related field
  • 5-8 years FPGA design experience, including Xilinx Vivado
  • Strong knowledge of System Verilog
  • Experience with RTL design for various signal processing blocks, including but not limited to equalizers, correlators, filters, FEC encoders and decoders
  • Proven track record to design and implement FPGA modules using System Verilog with simulation and testbench development
  • Work independently, take initiative, and take ownership of tasks and results
  • Strong written and verbal communication skills, ability to work with a geographically distributed team

What will help you on the job
  • Familiarity with Matlab
  • Experience with GitHub
  • Experience with developing code for legacy Viasat modem platforms
  • Familiarity with DVB-S2x and DVB-RCS2 standards
  • Understanding and knowledge of Satellite communication waveforms and standards

#LI-BBS


Salary range
$155,500.00 - $246,000.00 / annually.For specific work locations within San Jose, the San Francisco Bay area and New York City metropolitan area, the base pay range for this role is $193,500.00- $290,500.00/ annually
At Viasat, we consider many factors when it comes to compensation, including the scope of the position as well as your background and experience. Base pay may vary depending on job-related knowledge, skills, and experience. Additional cash or stock incentives may be provided as part of the compensation package, in addition to a range of medical, financial, and/or other benefits, dependent on the position offered. Learn more about Viasat's comprehensive benefit offerings that are focused on your holistic health and wellness at https://careers.viasat.com/benefits.
EEO Statement

Viasat is proud to be an equal opportunity employer, seeking to create a welcoming and diverse environment. All qualified applicants will receive consideration for employment without regard to race, color, religion, gender, gender identity or expression, sexual orientation, national origin, ancestry, physical or mental disability, medical condition, marital status, genetics, age, or veteran status or any other applicable legally protected status or characteristic. If you would like to request an accommodation on the basis of disability for completing this on-line application, please click here.

Qualifications:
  • Bachelor's Degree in Electrical Engineering, Computer Engineering or a related field
  • 5-8 years FPGA design experience, including Xilinx Vivado
  • Strong knowledge of System Verilog
  • Experience with RTL design for various signal processing blocks, including but not limited to equalizers, correlators, filters, FEC encoders and decoders
  • Proven track record to design and implement FPGA modules using System Verilog with simulation and testbench development
  • Work independently, take initiative, and take ownership of tasks and results
  • Strong written and verbal communication skills, ability to work with a geographically distributed team
Education:UNAVAILABLEEmployment Type: CONTRACTOR

What Viasat employees say

Pay

Benefits

Hours and flexibility

Workplace

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ViaSat logo

About ViaSat

Sourced by ZipRecruiter

At Viasat, we're on a mission to deliver connections with the capacity to change the world. For more than 35 years, Viasat has helped shape how consumers, businesses, governments and militaries around the globe communicate.

Industry

Telecommunications

Company size

5,001 - 10,000 Employees

Headquarters location

Carlsbad, CA, US

Year founded

1986

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