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Locum Asic Rtl Design Engineer Jobs in Virginia (NOW HIRING)

... of RTL design for FPGAs in VHDL or Verilog, or System Verilog - knowledge of all 3 strongly ... C++ programming * Mapping data processing algorithms to FPGAs using Vitis HLS * Implementing AI/ML ...

... of RTL design for FPGAs in VHDL or Verilog, or System Verilog - knowledge of all 3 strongly ... C++ programming * Mapping data processing algorithms to FPGAs using Vitis HLS * Implementing AI/ML ...

... of RTL design for FPGAs in VHDL or Verilog, or System Verilog - knowledge of all 3 strongly ... C++ programming * Mapping data processing algorithms to FPGAs using Vitis HLS * Implementing AI/ML ...

Sr. FPGA Engineer II

Chantilly, VA · On-site

$133K - $171K/yr

... ASIC-based image processing algorithms. * Experience in both creating IP from scratch in RTL and ... PCB design and schematic capture and layout with tools such as Altium Designer. * Active TS/SCI ...

Sr. FPGA Engineer II

Chantilly, VA · On-site

$133K - $171K/yr

... ASIC-based image processing algorithms * Experience in both creating IP from scratch in RTL and ... PCB design and schematic capture and layout with tools such as Altium Designer ADDITIONAL ...

Sr. FPGA Engineer II

Chantilly, VA · On-site

$107K - $146K/yr

... ASIC-based image processing algorithms * Experience in both creating IP from scratch in RTL and ... PCB design and schematic capture and layout with tools such as Altium Designer ADDITIONAL ...

Sr. FPGA Engineer II

Chantilly, VA · On-site

$143K - $214K/yr

... ASIC-based image processing algorithms * Experience in both creating IP from scratch in RTL and ... PCB design and schematic capture and layout with tools such as Altium Designer ADDITIONAL ...

Work closely with RTL and physical design to ensure clean DFT integration and timing closure * Work ... Strong experience in DFT for complex ASIC/SoC designs (typically 10+ years) * Proven ownership of ...

Principal FPGA Engineer

Ashburn, VA · On-site

$144K - $192K/yr

Principal FPGA Engineer - Onsite position Curtiss-Wright is seeking an experienced Principal FPGA ... Strong understanding of FPGA design flow, including RTL design (System Verilog, Verilog, or VHDL ...

Showing results 21-40

Locum Asic Rtl Design Engineer information

What is the difference between Locum Asic Rtl Design Engineer vs Contract Asic Rtl Design Engineer?

AspectLocum Asic Rtl Design EngineerContract Asic Rtl Design Engineer
CredentialsTypically requires relevant engineering degrees and RTL design experienceSimilar credentials, often with specific RTL design certifications
Work EnvironmentTemporary, short-term assignments often in multiple locationsProject-based roles, usually in a fixed location or remote
Employer UsageUsed by agencies or companies needing immediate, short-term expertiseEngaged by companies or staffing agencies for project-specific work

Both roles involve RTL design skills for ASIC development, but a Locum Asic Rtl Design Engineer typically fills short-term, temporary positions, often through staffing agencies, while a Contract Asic Rtl Design Engineer is engaged for specific projects with defined durations. The main difference lies in the nature and duration of employment, but both require similar technical credentials and work environments.

What are the most commonly searched types of Asic Rtl Design Engineer jobs in Virginia?

The most popular types of Asic Rtl Design Engineer jobs in Virginia are:

What job categories do people searching Locum Asic Rtl Design Engineer jobs in Virginia look for?

The top searched job categories for Locum Asic Rtl Design Engineer jobs in Virginia are:

What cities in Virginia are hiring for Locum Asic Rtl Design Engineer jobs?

Cities in Virginia with the most Locum Asic Rtl Design Engineer job openings:

Engineer

Fairfax, VA • On-site

Full-time

This job post has expired today. Applications are no longer accepted.


Job description

Founded in 1996, Logos Technologies LLC (Logos) is a diversified science, engineering and technology company, with headquarters in Northern Virginia. Logos specializes in the fields of advanced sensors, wide-area motion imagery, advanced analytics and processing of large, multisource datasets. We serve multiple government and commercial customers worldwide with wide-area persistent surveillance solutions that are critical to the success of their missions in national defense, public safety and border security, and humanitarian assistance.

Job Summary

Logos is searching for an FPGA developer to join a multidisciplinary team implementing state-of-the-art image processing and exploitation algorithms for airborne imaging sensor systems and supporting a diverse portfolio of image and signal processing capabilities. The successful candidate will have a strong mathematical background, experience with image processing algorithms, good programming abilities, and a desire to continuously improve and diversify their engineering skills. The position will be supported by appropriate supervision, training, and mentoring. Some travel supporting system design and flight testing will be required


  • Support existing FPGA Image processing designs with bug fixes, version upgrades, and new features as required
  • Work with System and Algorithm Engineers to partition new applications into components well suited for FPGA implementation
  • Develop new FPGA processing applications through the entire product lifecycle
  • Rigorously test FPGA components with simulation, hardware-in-the-loop and software-in-the-loop integration testing
  • Support field testing events for FPGA based systems

  • Bachelor’s degree from an accredited university in STEM field OR a combination of education and relevant experience.
  • 5+ years of RTL design for FPGAs in VHDL or Verilog, or System Verilog – knowledge of all 3 strongly preferred
  • Experience implementing signal or image processing algorithms into FPGA fabric
  • Experience with high-speed interfaces (ex. PCIe, CoaXPress, 10GbE) and DDR memory controllers
  • Experience with large FPGA designs on Kintex or Virtex devices including challenging timing closure
  • Experience with Xilinx Zynq, Versal, or Alveo system design
  • Matlab and Python programming
  • C++ programming
  • Mapping data processing algorithms to FPGAs using Vitis HLS
  • Implementing AI/ML inference algorithms using Vitis AI
  • Linux device driver development
  • Bit accurate validation of complex designs against algorithm models
  • Must be a U.S. citizen and able to obtain a security clearance
  • Demonstrated analytical problem solving

US Citizenship

Please apply on the Sparton Website.  www.sparton.com

How to Apply: Search jobs.

You can find this role posted under Logos Technologies, LLC

We look forward to receiving your application and resume.

US citizenship required.

To Apply for this Position: 

Go to the Sparton Home Page.

Search jobs.

You can find this role posted under Logos Technologies, LLC

We look forward to receiving your application and resume.