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Temporary Asic Rtl Design Engineer Jobs in Somerset, NJ

ASIC Engineer

New York, NY ยท On-site

$181K/yr

Have 4+ years practical experience in RTL design and verification * Experienced in ASIC design ... Interested in using software engineering techniques to improve the hardware design process, and ...

ASIC Engineer

New York, NY ยท On-site

$181K/yr

Have 4+ years practical experience in RTL design and verification * Experienced in ASIC design ... Interested in using software engineering techniques to improve the hardware design process, and ...

Hardware Engineer, RTL

New York, NY ยท On-site

$200K - $400K/yr

The Role As an RTL Design Engineer at Normal, you will design and verify the digital logic at the ... This work sits at the intersection of classical ASIC design, novel computing architectures, and a ...

ASIC Physical Design Engineer

New York, NY ยท On-site

$148K - $153K/yr

About the Position We are looking to hire an ASIC Physical Design Engineer to help us design, test ... You should be comfortable owning a PD flow end-to-end, but also able to read and write RTL and ...

ASIC Physical Design Engineer

New York, NY ยท On-site

$148K - $153K/yr

About the Position We are looking to hire an ASIC Physical Design Engineer to help us design, test ... You should be comfortable owning a PD flow end-to-end, but also able to read and write RTL and ...

... engineers with experience in both software and hardware design to help us build our FPGA or ASIC ... Your day-to-day work will predominantly involve OCaml & Hardcaml, for both RTL design and testing ...

... engineers with experience in both software and hardware design to help us build our FPGA or ASIC ... Your day-to-day work will predominantly involve OCaml & Hardcaml, for both RTL design and testing ...

Hardware Engineer, FPGA

New York, NY ยท On-site

$200K - $400K/yr

As our FPGA Design Engineer, you will own the bridge between RTL and physical silicon: bringing our physics-inspired ASIC designs to life on FPGA platforms for pre-silicon validation and early ...

... both RTL design and testing/integration. If you'd like to learn more, you can read about our ... Comfortable with a software programming language * Experienced with a Hardware Description (or ...

... both RTL design and testing/integration. If you'd like to learn more, you can read about our ... Comfortable with a software programming language * Experienced with a Hardware Description (or ...

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Temporary Asic Rtl Design Engineer information

See Somerset, NJ salary details

$99.3K

$158.7K

$213.4K

How much do temporary asic rtl design engineer jobs pay per year?

As of Sep 9, 2026, the average yearly pay for temporary asic rtl design engineer in Somerset, NJ is $158,689.00, according to ZipRecruiter salary data. Most workers in this role earn between $138,900.00 and $190,200.00 per year, depending on experience, location, and employer.

What is the difference between Temporary Asic Rtl Design Engineer vs Temporary FPGA Design Engineer?

AspectTemporary Asic Rtl Design EngineerTemporary FPGA Design Engineer
Primary FocusDesigning RTL code for ASIC chipsDesigning FPGA logic and configurations
Skills & CertificationsVerilog/VHDL, ASIC design flow, simulation toolsVerilog/VHDL, FPGA development tools, synthesis
Work EnvironmentSemiconductor companies, ASIC design teamsFPGA development labs, prototyping environments
Industry UsageUsed in high-volume chip manufacturingUsed for prototyping, testing, and low-volume products

Both roles involve RTL design using Verilog or VHDL, but the Temporary Asic Rtl Design Engineer focuses on ASIC chip development, while the Temporary FPGA Design Engineer specializes in FPGA-based prototyping and testing. The choice depends on whether the project aims for mass production or flexible, rapid development.

What are popular job titles related to Temporary Asic Rtl Design Engineer jobs in Somerset, NJ?

For Temporary Asic Rtl Design Engineer jobs in Somerset, NJ, the most frequently searched job titles are:

Infographic showing various Temporary Asic Rtl Design Engineer job openings in Somerset, NJ as of June 2026, with employment types broken down into 68% Full Time, 27% Part Time, and 5% Contract. Highlights an 99% Physical, and 1% Remote job distribution, with an average salary of $158,689 per year, or $76.3 per hour.

ASIC Engineer

New York, NY โ€ข On-site

Jane Street
Finance and Insuranceย โ€ขย 1 - 5K employees

$181K/yr

Full-time

Re-posted 13 days ago


Job description

About the Position

We are looking to hire an experienced ASIC Engineer to help us design, test and deploy advanced hardware designs. As part of our Ultra Low Latency team, you'll have the opportunity to collaborate with people in areas across the firm, including trading, networking and research infrastructure. We are looking for someone who can contribute to all of our projects and be happy to work on both FPGA-based and ASIC-based technologies.

We're big believers in the ability of tools to improve the productivity, reliability and day-to-day joy of hardware engineering. That's why we created Hardcaml, a hardware development toolchain embedded in OCaml. We don't expect you to know OCaml (we'll teach you here), but we are looking for hardware engineers who are excited about the advantages that better tools can bring, and are willing to try new things as a result.

About You
  • Have 4+ years practical experience in RTL design and verification
  • Experienced in ASIC design using either Synopsys or Cadence flows, including at least one of the following:
    • Front-end RTL design and synthesis
    • Back-end physical design
    • Verification (including formal)
  • Interested in using software engineering techniques to improve the hardware design process, and experience programming in some high-level languages (Python, C++, Java, Haskell, etc.)

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