ASIC Engineer
New York, NY ยท On-site
$181K/yr
Have 4+ years practical experience in RTL design and verification * Experienced in ASIC design ... Interested in using software engineering techniques to improve the hardware design process, and ...
New York, NY ยท On-site
$181K/yr
Have 4+ years practical experience in RTL design and verification * Experienced in ASIC design ... Interested in using software engineering techniques to improve the hardware design process, and ...
New York, NY ยท On-site
$181K/yr
Have 4+ years practical experience in RTL design and verification * Experienced in ASIC design ... Interested in using software engineering techniques to improve the hardware design process, and ...
New York, NY ยท On-site
$181K/yr
Have 4+ years practical experience in RTL design and verification * Experienced in ASIC design ... Interested in using software engineering techniques to improve the hardware design process, and ...
New York, NY ยท On-site
$181K/yr
Have 4+ years practical experience in RTL design and verification * Experienced in ASIC design ... Interested in using software engineering techniques to improve the hardware design process, and ...
New York, NY ยท On-site
$200K - $400K/yr
The Role As an RTL Design Engineer at Normal, you will design and verify the digital logic at the ... This work sits at the intersection of classical ASIC design, novel computing architectures, and a ...
New York, NY ยท On-site
$200K - $400K/yr
The Role As an RTL Design Engineer at Normal, you will design and verify the digital logic at the ... This work sits at the intersection of classical ASIC design, novel computing architectures, and a ...
Collaborate closely with RTL, design verification, DFT, STA, library, and package teams to resolve ... Strong experience in physical design for ASIC/SoC development, including successful implementation ...
Collaborate closely with RTL, design verification, DFT, STA, library, and package teams to resolve ... Strong experience in physical design for ASIC/SoC development, including successful implementation ...
New York, NY ยท On-site
$148K - $153K/yr
About the Position We are looking to hire an ASIC Physical Design Engineer to help us design, test ... You should be comfortable owning a PD flow end-to-end, but also able to read and write RTL and ...
New York, NY ยท On-site
$148K - $153K/yr
About the Position We are looking to hire an ASIC Physical Design Engineer to help us design, test ... You should be comfortable owning a PD flow end-to-end, but also able to read and write RTL and ...
New York, NY ยท On-site
$148K - $153K/yr
About the Position We are looking to hire an ASIC Physical Design Engineer to help us design, test ... You should be comfortable owning a PD flow end-to-end, but also able to read and write RTL and ...
New York, NY ยท On-site
$148K - $153K/yr
About the Position We are looking to hire an ASIC Physical Design Engineer to help us design, test ... You should be comfortable owning a PD flow end-to-end, but also able to read and write RTL and ...
New York, NY ยท On-site
... engineers with experience in both software and hardware design to help us build our FPGA or ASIC ... Your day-to-day work will predominantly involve OCaml & Hardcaml, for both RTL design and testing ...
New York, NY ยท On-site
... engineers with experience in both software and hardware design to help us build our FPGA or ASIC ... Your day-to-day work will predominantly involve OCaml & Hardcaml, for both RTL design and testing ...
New York, NY ยท On-site
... engineers with experience in both software and hardware design to help us build our FPGA or ASIC ... Your day-to-day work will predominantly involve OCaml & Hardcaml, for both RTL design and testing ...
New York, NY ยท On-site
... engineers with experience in both software and hardware design to help us build our FPGA or ASIC ... Your day-to-day work will predominantly involve OCaml & Hardcaml, for both RTL design and testing ...
New York, NY ยท On-site
$200K - $400K/yr
As our FPGA Design Engineer, you will own the bridge between RTL and physical silicon: bringing our physics-inspired ASIC designs to life on FPGA platforms for pre-silicon validation and early ...
New York, NY ยท On-site
$200K - $400K/yr
As our FPGA Design Engineer, you will own the bridge between RTL and physical silicon: bringing our physics-inspired ASIC designs to life on FPGA platforms for pre-silicon validation and early ...
Somerset, NJ ยท On-site
$143K - $147K/yr
Collaborate closely with RTL, design verification, DFT, STA, library, and package teams to resolve ... Strong experience in physical design for ASIC/SoC development, including successful implementation ...
Somerset, NJ ยท On-site
$143K - $147K/yr
Collaborate closely with RTL, design verification, DFT, STA, library, and package teams to resolve ... Strong experience in physical design for ASIC/SoC development, including successful implementation ...
New York, NY ยท On-site
... both RTL design and testing/integration. If you'd like to learn more, you can read about our ... Comfortable with a software programming language * Experienced with a Hardware Description (or ...
New York, NY ยท On-site
... both RTL design and testing/integration. If you'd like to learn more, you can read about our ... Comfortable with a software programming language * Experienced with a Hardware Description (or ...
New York, NY ยท On-site
... both RTL design and testing/integration. If you'd like to learn more, you can read about our ... Comfortable with a software programming language * Experienced with a Hardware Description (or ...
New York, NY ยท On-site
... both RTL design and testing/integration. If you'd like to learn more, you can read about our ... Comfortable with a software programming language * Experienced with a Hardware Description (or ...
Somerset, NJ ยท On-site
$127K - $175K/yr
... RTL, Standard cells, and similar approaches as necessary for both mixed signal ASIC and FPGA ... Digital Design Engineer or related occupation performing digital or mixed signal design and ...
Somerset, NJ ยท On-site
$127K - $175K/yr
... RTL, Standard cells, and similar approaches as necessary for both mixed signal ASIC and FPGA ... Digital Design Engineer or related occupation performing digital or mixed signal design and ...
Somerset, NJ ยท On-site
$127K - $175K/yr
... RTL, Standard cells, and similar approaches as necessary for both mixed signal ASIC and FPGA ... Digital Design Engineer or related occupation performing digital or mixed signal design and ...
Somerset, NJ ยท On-site
$127K - $175K/yr
... RTL, Standard cells, and similar approaches as necessary for both mixed signal ASIC and FPGA ... Digital Design Engineer or related occupation performing digital or mixed signal design and ...
... RTL. You'll work with FPGA, ASIC, or both technologies as a member of our integrated team. No ... Design engineers typically have training in computer architecture and digital logic design, and ...
... RTL. You'll work with FPGA, ASIC, or both technologies as a member of our integrated team. No ... Design engineers typically have training in computer architecture and digital logic design, and ...
... RTL. You'll work with FPGA, ASIC, or both technologies as a member of our integrated team. No ... Design engineers typically have training in computer architecture and digital logic design, and ...
... RTL. You'll work with FPGA, ASIC, or both technologies as a member of our integrated team. No ... Design engineers typically have training in computer architecture and digital logic design, and ...
New York, NY ยท On-site
$200K - $400K/yr
Sitting at the intersection of custom ASIC design and our hardware-algorithm co-designed systems ... Collaborate closely with RTL, architecture, and DFT teams to influence early floorplanning, macro ...
New York, NY ยท On-site
$200K - $400K/yr
Sitting at the intersection of custom ASIC design and our hardware-algorithm co-designed systems ... Collaborate closely with RTL, architecture, and DFT teams to influence early floorplanning, macro ...
New York, NY ยท On-site
$150K - $250K/yr
... engineering teams and external vendors to deliver high performance silicon on schedule. You will ... Coordinate handoffs and sign-off gates across architecture, RTL, DV, physical design ...
New York, NY ยท On-site
$150K - $250K/yr
... engineering teams and external vendors to deliver high performance silicon on schedule. You will ... Coordinate handoffs and sign-off gates across architecture, RTL, DV, physical design ...
Princeton, NJ ยท On-site
$63K - $84K/yr
... programmable device digital RTL design, design debug and characterization, and design documentation for transfer to manufacturing and user support. Success will rely heavily on efficient ...
Princeton, NJ ยท On-site
$63K - $84K/yr
... programmable device digital RTL design, design debug and characterization, and design documentation for transfer to manufacturing and user support. Success will rely heavily on efficient ...
Princeton, NJ ยท On-site
$63K - $84K/yr
... programmable device digital RTL design, design debug and characterization, and design documentation for transfer to manufacturing and user support. Success will rely heavily on efficient ...
Princeton, NJ ยท On-site
$63K - $84K/yr
... programmable device digital RTL design, design debug and characterization, and design documentation for transfer to manufacturing and user support. Success will rely heavily on efficient ...
$99.3K - $109.7K
16% of jobs
$109.7K - $120.1K
3% of jobs
$120.1K - $130.4K
4% of jobs
$133.5K is the 25th percentile. Wages below this are outliers.
$130.4K - $140.8K
6% of jobs
The median wage is $147.3K / yr.
$140.8K - $151.2K
33% of jobs
$151.2K - $161.6K
3% of jobs
$161.6K - $171.9K
2% of jobs
$178.8K is the 75th percentile. Wages above this are outliers.
$171.9K - $182.3K
12% of jobs
$182.3K - $192.7K
5% of jobs
$192.7K - $203K
4% of jobs
$203K - $213.4K
12% of jobs
$99.3K
$158.7K
$213.4K
| Aspect | Temporary Asic Rtl Design Engineer | Temporary FPGA Design Engineer |
|---|---|---|
| Primary Focus | Designing RTL code for ASIC chips | Designing FPGA logic and configurations |
| Skills & Certifications | Verilog/VHDL, ASIC design flow, simulation tools | Verilog/VHDL, FPGA development tools, synthesis |
| Work Environment | Semiconductor companies, ASIC design teams | FPGA development labs, prototyping environments |
| Industry Usage | Used in high-volume chip manufacturing | Used for prototyping, testing, and low-volume products |
Both roles involve RTL design using Verilog or VHDL, but the Temporary Asic Rtl Design Engineer focuses on ASIC chip development, while the Temporary FPGA Design Engineer specializes in FPGA-based prototyping and testing. The choice depends on whether the project aims for mass production or flexible, rapid development.
For Temporary Asic Rtl Design Engineer jobs in Somerset, NJ, the most frequently searched job titles are:

New York, NY โข On-site
$181K/yr
Full-time
Re-posted 13 days ago
We are looking to hire an experienced ASIC Engineer to help us design, test and deploy advanced hardware designs. As part of our Ultra Low Latency team, you'll have the opportunity to collaborate with people in areas across the firm, including trading, networking and research infrastructure. We are looking for someone who can contribute to all of our projects and be happy to work on both FPGA-based and ASIC-based technologies.
We're big believers in the ability of tools to improve the productivity, reliability and day-to-day joy of hardware engineering. That's why we created Hardcaml, a hardware development toolchain embedded in OCaml. We don't expect you to know OCaml (we'll teach you here), but we are looking for hardware engineers who are excited about the advantages that better tools can bring, and are willing to try new things as a result.
About YouIf you're a recruiting agency and want to partner with us, please reach out to agency-partnerships@janestreet.com.
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Finance and insurance
1,001 - 5,000 Employees
New York, NY, US
2000