ASIC/SoC RTL Design Engineer Location: Palo Alto, CA (Or potentially Burlington, MA) Length of Contract: 6 months+ (Temp-to-Perm) Ideal Start: 6/1/2026 Responsibilities : Own end-to-end design of ...
ASIC/SoC RTL Design Engineer Location: Palo Alto, CA (Or potentially Burlington, MA) Length of Contract: 6 months+ (Temp-to-Perm) Ideal Start: 6/1/2026 Responsibilities : Own end-to-end design of ...
ASIC Design Engineer Responsibilities: * Define and bring up FPGA platforms for pre-silicon ... Map ASIC RTL to FGPA while minimizing code base differences * Create and execute test plans for ...
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ASIC Design Engineer Responsibilities: * Define and bring up FPGA platforms for pre-silicon ... Map ASIC RTL to FGPA while minimizing code base differences * Create and execute test plans for ...
RTL Engineer (Ethernet)
San Francisco, CA · On-site
Sivaltech is hiring an experienced RTL Design Engineer with strong Ethernet expertise for a high ... Knowledge of ASIC/SoC design flow * Experience in clock/reset/power domain design * Exposure to ...
RTL Engineer (Ethernet)
San Francisco, CA · On-site
Sivaltech is hiring an experienced RTL Design Engineer with strong Ethernet expertise for a high ... Knowledge of ASIC/SoC design flow * Experience in clock/reset/power domain design * Exposure to ...
RTL Design Engineer - AI Tools
San Francisco, CA · Remote
$100 - $175/hr
Position: RTL Design Engineers Type: Contract Compensation: $100-$175/hour Location: Remote ... Experience with ASIC design flows and common EDA tools . * Ability to write clear design ...
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RTL Design Engineer - AI Tools
San Francisco, CA · Remote
$100 - $175/hr
Position: RTL Design Engineers Type: Contract Compensation: $100-$175/hour Location: Remote ... Experience with ASIC design flows and common EDA tools . * Ability to write clear design ...
ASIC Verification Engineer
Burlingame, CA · On-site
... 6-9 months - Temp-to-Perm Hours: 40 hours per week Scope: Client needs someone to lead ... Proficiency in SystemVerilog/UVM + RTL design concepts * Experience building self-checking ...
ASIC Verification Engineer
Burlingame, CA · On-site
... 6-9 months - Temp-to-Perm Hours: 40 hours per week Scope: Client needs someone to lead ... Proficiency in SystemVerilog/UVM + RTL design concepts * Experience building self-checking ...
Design Verification Engineer
$160K - $195K/yr
... engineers to resolve bugs Desired Skills and Experience Expertise in ... ASIC or FPGA RTL design verification Expertise in system Verilog, and UVM Strong experience in ...
Design Verification Engineer
$160K - $195K/yr
... engineers to resolve bugs Desired Skills and Experience Expertise in ... ASIC or FPGA RTL design verification Expertise in system Verilog, and UVM Strong experience in ...
... engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ...
... engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ...
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description In this highly visible role, you will be at the center of a silicon design group ...
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description In this highly visible role, you will be at the center of a silicon design group ...
Description We're looking for a Cellular ASIC Design Engineer, where you will architect and ... RTL implementation, to silicon bring-up and lab validation. You will collaborate closely with ...
Description We're looking for a Cellular ASIC Design Engineer, where you will architect and ... RTL implementation, to silicon bring-up and lab validation. You will collaborate closely with ...
Description We're looking for a Cellular ASIC Design Engineer, where you will architect and ... RTL implementation, to silicon bring-up and lab validation. You will collaborate closely with ...
Description We're looking for a Cellular ASIC Design Engineer, where you will architect and ... RTL implementation, to silicon bring-up and lab validation. You will collaborate closely with ...
Senior RTL Engineer, Interconnect Design
San Francisco, CA · On-site
$225K - $445K/yr
Within Hardware, the SoC design team works across architecture, RTL design, verification, physical design, performance, firmware, and systems engineering to deliver production-quality silicon for ...
Senior RTL Engineer, Interconnect Design
San Francisco, CA · On-site
$225K - $445K/yr
Within Hardware, the SoC design team works across architecture, RTL design, verification, physical design, performance, firmware, and systems engineering to deliver production-quality silicon for ...
FPGA Engineer
San Francisco, CA · On-site
$153K - $196K/yr
Good in understanding RTL Design and Digital concepts & Synthesis Strong experience with EDA tools ... of experience in ASIC or a related field, or a Master's Degree in Electrical or Computer ...
FPGA Engineer
San Francisco, CA · On-site
$153K - $196K/yr
Good in understanding RTL Design and Digital concepts & Synthesis Strong experience with EDA tools ... of experience in ASIC or a related field, or a Master's Degree in Electrical or Computer ...
Wireless Design Verification Engineer
San Francisco, CA · On-site
$160K - $195K/yr
As a Wireless Design Verification Engineer, you will be responsible for pre-silicon RTL ... Knowledge and experience of ASIC verification flows including test bench development, constrained ...
Wireless Design Verification Engineer
San Francisco, CA · On-site
$160K - $195K/yr
As a Wireless Design Verification Engineer, you will be responsible for pre-silicon RTL ... Knowledge and experience of ASIC verification flows including test bench development, constrained ...
PHY Design Verification Engineer
San Francisco, CA · On-site
$160K - $195K/yr
As a PHY Design Verification Engineer, you will be responsible for pre-silicon RTL verification of ... Excellent knowledge and experience of ASIC verification flows including test bench development ...
PHY Design Verification Engineer
San Francisco, CA · On-site
$160K - $195K/yr
As a PHY Design Verification Engineer, you will be responsible for pre-silicon RTL verification of ... Excellent knowledge and experience of ASIC verification flows including test bench development ...
Hardware Engineer
San Bruno, CA · On-site
$147K - $194K/yr
Working in a small, highly collaborative group, you will contribute directly to RTL design ... Familiarity with ASIC or FPGA design flows * Proficiency in Python for scripting and automation
Hardware Engineer
San Bruno, CA · On-site
$147K - $194K/yr
Working in a small, highly collaborative group, you will contribute directly to RTL design ... Familiarity with ASIC or FPGA design flows * Proficiency in Python for scripting and automation
Physical Design Engineer
San Francisco, CA · On-site
$266K - $445K/yr
You'll work closely with RTL designers to define and execute on physical design strategies. You ... and ASIC partners Qualifications: * BS w/ 4+ or MS with 2+ years or PhD with 0-1 year(s) of ...
Physical Design Engineer
San Francisco, CA · On-site
$266K - $445K/yr
You'll work closely with RTL designers to define and execute on physical design strategies. You ... and ASIC partners Qualifications: * BS w/ 4+ or MS with 2+ years or PhD with 0-1 year(s) of ...
... RTL Design and DV teams within Apple's HWTech organization. This role leverages advanced ... ASIC workflows Experience working directly with design and verification engineers to define ...
... RTL Design and DV teams within Apple's HWTech organization. This role leverages advanced ... ASIC workflows Experience working directly with design and verification engineers to define ...
RTL & Co-design Engineer (junior)
San Francisco, CA · On-site
$225K - $445K/yr
About the Role We're looking for a RTL Engineer to design and implement key compute, memory, and interconnect components for our custom AI accelerator. You'll work closely with architecture ...
RTL & Co-design Engineer (junior)
San Francisco, CA · On-site
$225K - $445K/yr
About the Role We're looking for a RTL Engineer to design and implement key compute, memory, and interconnect components for our custom AI accelerator. You'll work closely with architecture ...
Digital IC Design Engineer Intern
Fremont, CA · On-site
$35/hr
Micro-architecture design and RTL implementation of: * Low-power digital signal processors * Low ... Temporary Employees & Interns excluded
Digital IC Design Engineer Intern
Fremont, CA · On-site
$35/hr
Micro-architecture design and RTL implementation of: * Low-power digital signal processors * Low ... Temporary Employees & Interns excluded
Hardware Design Engineer
$180K - $250K/yr
We're looking for a seasoned RTL design expert with over 5 years of hands-on experience, including successful tape-outs of multiple chips. Your expertise will drive the creation of advanced RL ...
Quick apply
Hardware Design Engineer
$180K - $250K/yr
We're looking for a seasoned RTL design expert with over 5 years of hands-on experience, including successful tape-outs of multiple chips. Your expertise will drive the creation of advanced RL ...
Temporary Asic Rtl Design Engineer information
See Berkeley, CA salary details
$115.1K - $127.1K
16% of jobs
$127.1K - $139.1K
3% of jobs
$139.1K - $151.2K
4% of jobs
$154.7K is the 25th percentile. Wages below this are outliers.
$151.2K - $163.2K
6% of jobs
The median wage is $170.7K / yr.
$163.2K - $175.2K
33% of jobs
$175.2K - $187.2K
3% of jobs
$187.2K - $199.2K
2% of jobs
$207.2K is the 75th percentile. Wages above this are outliers.
$199.2K - $211.3K
12% of jobs
$211.3K - $223.3K
5% of jobs
$223.3K - $235.3K
4% of jobs
$235.3K - $247.3K
12% of jobs
$115.1K
$183.9K
$247.3K
How much do temporary asic rtl design engineer jobs pay per year?
What is the difference between Temporary Asic Rtl Design Engineer vs Temporary FPGA Design Engineer?
| Aspect | Temporary Asic Rtl Design Engineer | Temporary FPGA Design Engineer |
|---|---|---|
| Primary Focus | Designing RTL code for ASIC chips | Designing FPGA logic and configurations |
| Skills & Certifications | Verilog/VHDL, ASIC design flow, simulation tools | Verilog/VHDL, FPGA development tools, synthesis |
| Work Environment | Semiconductor companies, ASIC design teams | FPGA development labs, prototyping environments |
| Industry Usage | Used in high-volume chip manufacturing | Used for prototyping, testing, and low-volume products |
Both roles involve RTL design using Verilog or VHDL, but the Temporary Asic Rtl Design Engineer focuses on ASIC chip development, while the Temporary FPGA Design Engineer specializes in FPGA-based prototyping and testing. The choice depends on whether the project aims for mass production or flexible, rapid development.
Job description
Title: ASIC/SoC RTL Design Engineer
Location: Palo Alto, CA (Or potentially Burlington, MA)
Length of Contract: 6 months+ (Temp-to-Perm)
Ideal Start: 6/1/2026
Responsibilities :
Own end-to-end design of complex SoC subsystems, driving architecture, RTL implementation, and tapeout. Focus on high-performance Datapath, PPA optimization, and cross-functional integration across silicon, firmware, and system teams.
Must haves:
- 8 12+ years in ASIC/SoC digital design with hands-on RTL ownership
- Strong SystemVerilog/Verilog RTL development (Datapath, control logic, state machines)
- Proven experience owning subsystems from architecture RTL tapeout
- Deep understanding of PPA tradeoffs, timing closure, clock/reset, and power-aware design
- Experience designing high throughput Datapath (buffering, arbitration, memory hierarchy)
- Background in advanced nodes ( 28nm) and cross-functional collaboration (verification, systems, firmware)
Pluses:
- Experience with compute-intensive pipelines (DSP, AI, beamforming, MAC Datapath)
- Exposure to sensor / imaging systems (e.g., ultrasound, data acquisition)
- Experience with programmable compute blocks (AI accelerators, MPUs, eFPGA)
About Oxford Global Resources
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Oxford Global Resources delivers tailored solutions for any technical challenges you face using our partnership-first approach. We specialize in workforce mobilization, digital transformation, and modern enterprise. We are committed to providing you with The Right Talent. Right Now. In 1984, we started Oxford with a handful of employees in a converted schoolhouse in Reading, Massachusetts. The people that shape our organization are some of the best in the industry. They are dedicated to making an impact and are with you every step of the way. We strive to meet the most pressing needs, solve the most complex problems, and go beyond expectations for our clients and our consultants. Together, we drive great outcomes. Whether you’d like to join the thousands of professionals who trust Oxford to advance their careers or partner with us to solve a challenge your business is facing, contact us at any of our 35 global offices.
Industry
Recruiting and staffing services
Company size
501 - 1,000 Employees
Headquarters location
Beverly, MA, US
Year founded
1984