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Temporary Asic Rtl Design Engineer Jobs in Berkeley, CA

Sivaltech is hiring an experienced RTL Design Engineer with strong Ethernet expertise for a high ... Knowledge of ASIC/SoC design flow * Experience in clock/reset/power domain design * Exposure to ...

Position: RTL Design Engineers Type: Contract Compensation: $100-$175/hour Location: Remote ... Experience with ASIC design flows and common EDA tools . * Ability to write clear design ...

... engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ...

... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description In this highly visible role, you will be at the center of a silicon design group ...

FPGA Engineer

San Francisco, CA · On-site

$153K - $196K/yr

Good in understanding RTL Design and Digital concepts & Synthesis Strong experience with EDA tools ... of experience in ASIC or a related field, or a Master's Degree in Electrical or Computer ...

PHY Design Verification Engineer

San Francisco, CA · On-site

$160K - $195K/yr

As a PHY Design Verification Engineer, you will be responsible for pre-silicon RTL verification of ... Excellent knowledge and experience of ASIC verification flows including test bench development ...

Hardware Engineer

San Bruno, CA · On-site

$147K - $194K/yr

Working in a small, highly collaborative group, you will contribute directly to RTL design ... Familiarity with ASIC or FPGA design flows * Proficiency in Python for scripting and automation

You'll work closely with RTL designers to define and execute on physical design strategies. You ... and ASIC partners Qualifications: * BS w/ 4+ or MS with 2+ years or PhD with 0-1 year(s) of ...

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Temporary Asic Rtl Design Engineer information

See Berkeley, CA salary details

$115.1K

$183.9K

$247.3K

How much do temporary asic rtl design engineer jobs pay per year?

As of Jun 27, 2026, the average yearly pay for temporary asic rtl design engineer in Berkeley, CA is $183,905.00, according to ZipRecruiter salary data. Most workers in this role earn between $161,000.00 and $220,400.00 per year, depending on experience, location, and employer.

What is the difference between Temporary Asic Rtl Design Engineer vs Temporary FPGA Design Engineer?

AspectTemporary Asic Rtl Design EngineerTemporary FPGA Design Engineer
Primary FocusDesigning RTL code for ASIC chipsDesigning FPGA logic and configurations
Skills & CertificationsVerilog/VHDL, ASIC design flow, simulation toolsVerilog/VHDL, FPGA development tools, synthesis
Work EnvironmentSemiconductor companies, ASIC design teamsFPGA development labs, prototyping environments
Industry UsageUsed in high-volume chip manufacturingUsed for prototyping, testing, and low-volume products

Both roles involve RTL design using Verilog or VHDL, but the Temporary Asic Rtl Design Engineer focuses on ASIC chip development, while the Temporary FPGA Design Engineer specializes in FPGA-based prototyping and testing. The choice depends on whether the project aims for mass production or flexible, rapid development.

What are the most commonly searched types of Asic Rtl Design Engineer jobs in Berkeley, CA? The most popular types of Asic Rtl Design Engineer jobs in Berkeley, CA are:
What cities near Berkeley, CA are hiring for Temporary Asic Rtl Design Engineer jobs? Cities near Berkeley, CA with the most Temporary Asic Rtl Design Engineer job openings:
ASIC/ SoC RTL Design Engineer

ASIC/ SoC RTL Design Engineer

Oxford Global Resources

Burlingame, CA • On-site

Other

Posted 22 days ago


Job description

Title: ASIC/SoC RTL Design Engineer

Location: Palo Alto, CA (Or potentially Burlington, MA)

Length of Contract: 6 months+ (Temp-to-Perm)

Ideal Start: 6/1/2026

Responsibilities :

Own end-to-end design of complex SoC subsystems, driving architecture, RTL implementation, and tapeout. Focus on high-performance Datapath, PPA optimization, and cross-functional integration across silicon, firmware, and system teams.

Must haves:

  • 8 12+ years in ASIC/SoC digital design with hands-on RTL ownership
  • Strong SystemVerilog/Verilog RTL development (Datapath, control logic, state machines)
  • Proven experience owning subsystems from architecture RTL tapeout
  • Deep understanding of PPA tradeoffs, timing closure, clock/reset, and power-aware design
  • Experience designing high throughput Datapath (buffering, arbitration, memory hierarchy)
  • Background in advanced nodes ( 28nm) and cross-functional collaboration (verification, systems, firmware)

Pluses:

  • Experience with compute-intensive pipelines (DSP, AI, beamforming, MAC Datapath)
  • Exposure to sensor / imaging systems (e.g., ultrasound, data acquisition)
  • Experience with programmable compute blocks (AI accelerators, MPUs, eFPGA)

Oxford Global Resources logo

About Oxford Global Resources

Sourced by ZipRecruiter

Oxford Global Resources delivers tailored solutions for any technical challenges you face using our partnership-first approach. We specialize in workforce mobilization, digital transformation, and modern enterprise. We are committed to providing you with The Right Talent. Right Now. In 1984, we started Oxford with a handful of employees in a converted schoolhouse in Reading, Massachusetts. The people that shape our organization are some of the best in the industry. They are dedicated to making an impact and are with you every step of the way. We strive to meet the most pressing needs, solve the most complex problems, and go beyond expectations for our clients and our consultants. Together, we drive great outcomes. Whether you’d like to join the thousands of professionals who trust Oxford to advance their careers or partner with us to solve a challenge your business is facing, contact us at any of our 35 global offices.

Industry

Recruiting and staffing services

Company size

501 - 1,000 Employees

Headquarters location

Beverly, MA, US

Year founded

1984

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