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Temporary Asic Rtl Design Engineer Jobs in Berkeley, CA

Sivaltech

RTL Engineer (Ethernet)

San Francisco, CA · On-site

Sivaltech is hiring an experienced RTL Design Engineer with strong Ethernet expertise for a high ... Knowledge of ASIC/SoC design flow * Experience in clock/reset/power domain design * Exposure to ...

Mercor

RTL Design Engineer - AI Tools

San Francisco, CA · Remote

$100 - $175/hr

Position: RTL Design Engineers Type: Contract Compensation: $100-$175/hour Location: Remote ... Experience with ASIC design flows and common EDA tools . * Ability to write clear design ...

Apple

Wireless RTL Design Engineer

San Francisco, CA · On-site

... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description In this highly visible role, you will be at the center of a silicon design group ...

Apple

Wireless RTL Design Engineer

San Francisco, CA · On-site

... engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ...

Apple

PHY Design Verification Engineer

San Francisco, CA · On-site

$160K - $195K/yr

As a PHY Design Verification Engineer, you will be responsible for pre-silicon RTL verification of ... Excellent knowledge and experience of ASIC verification flows including test bench development ...

Apple

PHY Design Verification Engineer

San Francisco, CA · On-site

$160K - $195K/yr

As a PHY Design Verification Engineer, you will be responsible for pre-silicon RTL verification of ... Excellent knowledge and experience of ASIC verification flows including test bench development ...

femtoAI

Hardware Engineer

San Bruno, CA · On-site

$147K - $194K/yr

Working in a small, highly collaborative group, you will contribute directly to RTL design ... Familiarity with ASIC or FPGA design flows * Proficiency in Python for scripting and automation

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All JobsAsic Rtl Design Engineer JobsTemporary Asic Rtl Design Engineer JobsTemporary Asic Rtl Design Engineer Jobs in Berkeley, CA

Temporary Asic Rtl Design Engineer information

See Berkeley, CA salary details

$115.1K

$183.9K

$247.3K

How much do temporary asic rtl design engineer jobs pay per year?

As of Jul 26, 2026, the average yearly pay for temporary asic rtl design engineer in Berkeley, CA is $183,905.00, according to ZipRecruiter salary data. Most workers in this role earn between $161,000.00 and $220,400.00 per year, depending on experience, location, and employer.

What is the difference between Temporary Asic Rtl Design Engineer vs Temporary FPGA Design Engineer?

AspectTemporary Asic Rtl Design EngineerTemporary FPGA Design Engineer
Primary FocusDesigning RTL code for ASIC chipsDesigning FPGA logic and configurations
Skills & CertificationsVerilog/VHDL, ASIC design flow, simulation toolsVerilog/VHDL, FPGA development tools, synthesis
Work EnvironmentSemiconductor companies, ASIC design teamsFPGA development labs, prototyping environments
Industry UsageUsed in high-volume chip manufacturingUsed for prototyping, testing, and low-volume products

Both roles involve RTL design using Verilog or VHDL, but the Temporary Asic Rtl Design Engineer focuses on ASIC chip development, while the Temporary FPGA Design Engineer specializes in FPGA-based prototyping and testing. The choice depends on whether the project aims for mass production or flexible, rapid development.

What are the most commonly searched types of Asic Rtl Design Engineer jobs in Berkeley, CA? The most popular types of Asic Rtl Design Engineer jobs in Berkeley, CA are:
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Temporary Asic Rtl Design Engineer jobs near you

Lead ASIC RTL Design Engineer

4 Staffing Corp

San Francisco, CA • On-site, Remote

Full-time

This job post has expired today. Applications are no longer accepted.

Job description

About the job Lead ASIC RTL Design Engineer
Lead ASIC RTL Design Engineer - Remote (U.S.) - No visa sponsorship
Role Summary
Our client, a leader in AI Compute is seeking a senior-level ASIC design engineer to drive the development of high-performance silicon components used in advanced compute platforms. This individual will take ownership of key IP blocks from early architectural definition through RTL delivery and signoff, working closely with cross-functional teams to meet aggressive performance, power, and area goals. The role combines hands-on design work with technical leadership and mentorship.
Core Responsibilities
Architecture & RTL Development

  • Define microarchitecture for complex subsystems and document design specifications
  • Implement high-quality, reusable RTL in System Verilog with clear interface definitions and design intent
  • Incorporate assertions and design-for-debug features within RTL
Design Ownership & Implementation
  • Lead front-end design activities including linting, clock/reset domain analysis, and synthesis readiness
  • Collaborate with physical design teams on floor planning, timing closure, and implementation tradeoffs
  • Take responsibility for achieving performance, power, and area (PPA) targets for assigned blocks
High-Speed Interfaces & Memory Systems
  • Design and integrate high-bandwidth interfaces and interconnects (e.g., AMBA-based protocols, coherent fabrics)
  • Work on memory subsystem integration, including external DRAM and high-throughput memory solutions
  • Coordinate with internal teams and third-party IP providers to ensure proper integration and functionality
Engineering Processes & Tooling
  • Establish and maintain RTL design standards, reusable components, and signoff criteria
  • Contribute to automation and workflow improvements using scripting and build systems (Python, Tcl, CI pipelines)
Collaboration & System Integration
  • Partner with verification teams on test planning, coverage goals, and model alignment
  • Work with architecture and performance engineering to validate design intent against system-level expectations
  • Support silicon bring-up, debugging, and downstream customer or system integration efforts
Technical Leadership
  • Mentor less experienced engineers and provide guidance on design best practices
  • Lead design reviews and help drive key technical decisions across teams
  • Advocate for scalable, efficient, and high-quality engineering solutions
Basic Qualifications
  • Bachelor's or Master's degree in Electrical or Computer Engineering (or similar field)
  • 8+ years of experience in ASIC or SoC RTL design for complex, high-speed devices
  • Demonstrated experience delivering designs from concept through RTL implementation and tape out readiness
  • Strong System Verilog expertise, including clocking strategies, reset design, and domain crossing considerations
  • Hands-on experience with front-end design tools and flows (linting, CDC analysis, synthesis, timing analysis, DFT)
  • Familiarity with multiple high-speed technologies such as memory interfaces, interconnect protocols, or compute data paths
  • Strong communication skills with the ability to lead technical discussions and document designs clearly
Preferred Experience
  • Exposure to AI/ML hardware or high-performance compute architectures
  • Knowledge of formal verification techniques and assertion-based design
  • Experience with power optimization methods (e.g., clock gating, power intent formats like UPF/CPF)
  • Familiarity working alongside verification environments (UVM, Python-based frameworks, or similar)
  • Understanding of modern processor subsystems, coherence models, or custom tool flows

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