We're looking for hardware engineers with hands-on experience in chip design workflows--ideally ... SPECIALTY: DI (Design Integration, RTL, Architecture) * Proven track record of developing ...
Quick apply
We're looking for hardware engineers with hands-on experience in chip design workflows--ideally ... SPECIALTY: DI (Design Integration, RTL, Architecture) * Proven track record of developing ...
... and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description In this highly visible role, you will be at the center of a ...
... and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description In this highly visible role, you will be at the center of a ...
Senior FPGA Engineer
Pleasanton, CA · On-site
$130K - $155K/yr
Our team of engineers, scientists, software developers, and operations professionals works together ... Understanding of practical RTL design issues such as latency, jitter, metastability, setup/hold ...
Senior FPGA Engineer
Pleasanton, CA · On-site
$130K - $155K/yr
Our team of engineers, scientists, software developers, and operations professionals works together ... Understanding of practical RTL design issues such as latency, jitter, metastability, setup/hold ...
Software Engineer, ASIC
South San Francisco, CA · On-site
$199K/yr
As a Software Engineer, ASIC, you will integrate tightly with teams across the company, and span ... Build and maintain scalable EDA compute infrastructure for analog and digital chip design * Develop ...
Software Engineer, ASIC
South San Francisco, CA · On-site
$199K/yr
As a Software Engineer, ASIC, you will integrate tightly with teams across the company, and span ... Build and maintain scalable EDA compute infrastructure for analog and digital chip design * Develop ...
Senior FPGA Engineer
$130K - $155K/yr
Our team of engineers, scientists, software developers, and operations professionals works together ... Understanding of practical RTL design issues such as latency, jitter, metastability, setup/hold ...
Senior FPGA Engineer
$130K - $155K/yr
Our team of engineers, scientists, software developers, and operations professionals works together ... Understanding of practical RTL design issues such as latency, jitter, metastability, setup/hold ...
Senior FPGA Engineer
Pleasanton, CA · On-site
$130K - $155K/yr
Our team of engineers, scientists, software developers, and operations professionals works together ... Understanding of practical RTL design issues such as latency, jitter, metastability, setup/hold ...
Quick apply
Senior FPGA Engineer
Pleasanton, CA · On-site
$130K - $155K/yr
Our team of engineers, scientists, software developers, and operations professionals works together ... Understanding of practical RTL design issues such as latency, jitter, metastability, setup/hold ...
... and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description In this highly visible role, you will be at the center of a ...
... and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description In this highly visible role, you will be at the center of a ...
Wireless SOC FW Engineer
San Francisco, CA · On-site
... and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description In this highly visible role, you will be at the center of a ...
Wireless SOC FW Engineer
San Francisco, CA · On-site
... and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description In this highly visible role, you will be at the center of a ...
Wireless SOC FW Engineer
San Francisco, CA · On-site
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. In this highly visible role, you will be at the center of a silicon design group with a ...
Wireless SOC FW Engineer
San Francisco, CA · On-site
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. In this highly visible role, you will be at the center of a silicon design group with a ...
All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration ...
All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration ...
Design Verification Intern
Burlingame, CA · On-site
$45 - $60/hr
... RTL Design, ML systems, or performance engineering. * Exposure to assembly or low-level code ... The hourly rate for this temporary internship position is $45.00/hour to $60.00/hour. The actual ...
Quick apply
Design Verification Intern
Burlingame, CA · On-site
$45 - $60/hr
... RTL Design, ML systems, or performance engineering. * Exposure to assembly or low-level code ... The hourly rate for this temporary internship position is $45.00/hour to $60.00/hour. The actual ...
Design Verification Intern
Burlingame, CA · On-site
$45 - $60/hr
... RTL Design, ML systems, or performance engineering. * Exposure to assembly or low-level code ... The hourly rate for this temporary internship position is $45.00/hour to $60.00/hour. The actual ...
Design Verification Intern
Burlingame, CA · On-site
$45 - $60/hr
... RTL Design, ML systems, or performance engineering. * Exposure to assembly or low-level code ... The hourly rate for this temporary internship position is $45.00/hour to $60.00/hour. The actual ...
Design Verification Intern
$45 - $60/hr
... RTL Design, ML systems, or performance engineering. * Exposure to assembly or low-level code ... The hourly rate for this temporary internship position is $45.00/hour to $60.00/hour. The actual ...
Design Verification Intern
$45 - $60/hr
... RTL Design, ML systems, or performance engineering. * Exposure to assembly or low-level code ... The hourly rate for this temporary internship position is $45.00/hour to $60.00/hour. The actual ...
Hardware Tools Engineer
San Francisco, CA · On-site
$225K - $445K/yr
The work spans software engineering, compiler concepts, and practical hardware workflows, with ... Familiarity with digital design concepts and the ability to read RTL (Verilog/SystemVerilog) or ...
Hardware Tools Engineer
San Francisco, CA · On-site
$225K - $445K/yr
The work spans software engineering, compiler concepts, and practical hardware workflows, with ... Familiarity with digital design concepts and the ability to read RTL (Verilog/SystemVerilog) or ...
RFIC Layout Engineer
San Francisco, CA · On-site
... VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description As an RFIC Layout Designer, you will be a key member of a RFIC team ...
RFIC Layout Engineer
San Francisco, CA · On-site
... VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description As an RFIC Layout Designer, you will be a key member of a RFIC team ...
All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration ...
All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration ...
All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration ...
All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration ...
This role is ideal for an engineer who is energized by deep tech, thrives in cross-functional ... Strong experience with end-to-end FPGA and MPSoC design, including architecture, RTL development ...
This role is ideal for an engineer who is energized by deep tech, thrives in cross-functional ... Strong experience with end-to-end FPGA and MPSoC design, including architecture, RTL development ...
Staff FPGA Engineer
Pleasanton, CA · On-site
$150K - $180K/yr
Our team of engineers, scientists, software developers, and operations professionals works together ... Understanding of practical RTL design issues such as latency, jitter, metastability, setup/hold ...
Staff FPGA Engineer
Pleasanton, CA · On-site
$150K - $180K/yr
Our team of engineers, scientists, software developers, and operations professionals works together ... Understanding of practical RTL design issues such as latency, jitter, metastability, setup/hold ...
Staff FPGA Engineer
Pleasanton, CA · On-site
$150K - $180K/yr
Our team of engineers, scientists, software developers, and operations professionals works together ... Understanding of practical RTL design issues such as latency, jitter, metastability, setup/hold ...
Quick apply
Staff FPGA Engineer
Pleasanton, CA · On-site
$150K - $180K/yr
Our team of engineers, scientists, software developers, and operations professionals works together ... Understanding of practical RTL design issues such as latency, jitter, metastability, setup/hold ...
Temporary Asic Rtl Design Engineer information
See Berkeley, CA salary details
$115.1K - $127.1K
16% of jobs
$127.1K - $139.1K
3% of jobs
$139.1K - $151.2K
4% of jobs
$154.7K is the 25th percentile. Wages below this are outliers.
$151.2K - $163.2K
6% of jobs
The median wage is $170.7K / yr.
$163.2K - $175.2K
33% of jobs
$175.2K - $187.2K
3% of jobs
$187.2K - $199.2K
2% of jobs
$207.2K is the 75th percentile. Wages above this are outliers.
$199.2K - $211.3K
12% of jobs
$211.3K - $223.3K
5% of jobs
$223.3K - $235.3K
4% of jobs
$235.3K - $247.3K
12% of jobs
$115.1K
$183.9K
$247.3K
How much do temporary asic rtl design engineer jobs pay per year?
As of Jun 27, 2026, the average yearly pay for temporary asic rtl design engineer in Berkeley, CA is $183,905.00, according to ZipRecruiter salary data. Most workers in this role earn between $161,000.00 and $220,400.00 per year, depending on experience, location, and employer.
What is the difference between Temporary Asic Rtl Design Engineer vs Temporary FPGA Design Engineer?
| Aspect | Temporary Asic Rtl Design Engineer | Temporary FPGA Design Engineer |
|---|---|---|
| Primary Focus | Designing RTL code for ASIC chips | Designing FPGA logic and configurations |
| Skills & Certifications | Verilog/VHDL, ASIC design flow, simulation tools | Verilog/VHDL, FPGA development tools, synthesis |
| Work Environment | Semiconductor companies, ASIC design teams | FPGA development labs, prototyping environments |
| Industry Usage | Used in high-volume chip manufacturing | Used for prototyping, testing, and low-volume products |
Both roles involve RTL design using Verilog or VHDL, but the Temporary Asic Rtl Design Engineer focuses on ASIC chip development, while the Temporary FPGA Design Engineer specializes in FPGA-based prototyping and testing. The choice depends on whether the project aims for mass production or flexible, rapid development.
What are the most commonly searched types of Asic Rtl Design Engineer jobs in Berkeley, CA? The most popular types of Asic Rtl Design Engineer jobs in Berkeley, CA are:
What cities near Berkeley, CA are hiring for Temporary Asic Rtl Design Engineer jobs? Cities near Berkeley, CA with the most Temporary Asic Rtl Design Engineer job openings:
Full-time
Posted 23 days ago
Job description
We’re looking for hardware engineers with hands-on experience in chip design workflows—ideally those who have contributed to real-world tapeouts at companies like Apple, NVIDIA, Etched, or leading EDA vendors such as Synopsys or Cadence. Candidates with exposure to AI-for-chip-design initiatives or a strong understanding of modern ML workflows will stand out.
Responsibilities
- Drive direction and technical leadership across our multi-agent platform and domain-specific hardware knowledge base.
- Bring a deep understanding of chip design workflows and help shape product roadmap with real-world context.
- Integrate seamlessly into customer pipelines across RTL, PD, and architectural stages.
- Track evolving trends in both semiconductor design and AI-assisted design automation.
- Create internal benchmarks and datasets to rigorously evaluate system performance across RTL, PD, and architectural use cases.
Qualifications
- Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a related discipline (interns may be considered for their flair).
- Hands-on experience in a semiconductor or EDA environment (e.g., NVIDIA, AMD, Intel, Synopsys, Cadence), 1+ years of full-time experience required, 3+ years preferred.
- Proficiency in scripting (Python, Bash) and experience with automation or tooling for design verification or integration.
SPECIALTY: DI (Design Integration, RTL, Architecture)
- Proven track record of developing architectures and RTL for hardware blocks or IP.
- Experience with SystemVerilog, Verilog & SoC design methodologies.
SPECIALTY: PD (Physical Design)
- Part of leading edge tapeouts (7nm or smaller). Worked on at least one of synthesis, floor planning, place-and-route, physical verification, and timing.
- Familiar with one of Genus, Innovus, Tempus, Mentor Calibre, Synopsys IC Compiler, or other relevant EDA CAD tool (and associated TCL).
Preferred Experience
- Experience on AI-for-chip-design initiatives (e.g., at Synopsys, NVIDIA, GoogleDeepMind).
- Understanding of DFT, power optimization techniques, or low-power design flows.
- Experience on an IP development team, developing PCIe, PHY, LPDOR, MemoryControllers, NoC, CPU subsystems, or similar.
About Brahma Consulting Group
Sourced by ZipRecruiter
Industry
Recruiting and staffing services
Company size
11 - 50 Employees
Headquarters location
Sacramento, CA, US
Year founded
2021