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Temporary Asic Rtl Design Engineer Jobs in Fremont, CA

CYNET SYSTEMS

ASIC/RTL Design Engineer 2

San Jose, CA · On-site

$60 - $62/hr

Hands-on experience in industry ASIC design flow including RTL coding, debugging/verification, and supporting synthesis and timing closure. * Working knowledge of Client cores and other I/O standard ...

TetraMem INC

ASIC RTL/SoC Design Engineer

Fremont, CA · On-site

Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...

TetraMem INC

ASIC RTL/SoC Design Engineer

Fremont, CA · On-site

Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...

TetraMem Inc

ASIC RTL/SoC Design Engineer

San Jose, CA · On-site

$110K - $300K/yr

Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...

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All JobsAsic Rtl Design Engineer JobsTemporary Asic Rtl Design Engineer JobsTemporary Asic Rtl Design Engineer Jobs in Fremont, CA

Temporary Asic Rtl Design Engineer information

See Fremont, CA salary details

$102.9K

$164.4K

$221.1K

How much do temporary asic rtl design engineer jobs pay per year?

As of Aug 5, 2026, the average yearly pay for temporary asic rtl design engineer in Fremont, CA is $164,414.00, according to ZipRecruiter salary data. Most workers in this role earn between $143,900.00 and $197,000.00 per year, depending on experience, location, and employer.

What is the difference between Temporary Asic Rtl Design Engineer vs Temporary FPGA Design Engineer?

AspectTemporary Asic Rtl Design EngineerTemporary FPGA Design Engineer
Primary FocusDesigning RTL code for ASIC chipsDesigning FPGA logic and configurations
Skills & CertificationsVerilog/VHDL, ASIC design flow, simulation toolsVerilog/VHDL, FPGA development tools, synthesis
Work EnvironmentSemiconductor companies, ASIC design teamsFPGA development labs, prototyping environments
Industry UsageUsed in high-volume chip manufacturingUsed for prototyping, testing, and low-volume products

Both roles involve RTL design using Verilog or VHDL, but the Temporary Asic Rtl Design Engineer focuses on ASIC chip development, while the Temporary FPGA Design Engineer specializes in FPGA-based prototyping and testing. The choice depends on whether the project aims for mass production or flexible, rapid development.

What are popular job titles related to Temporary Asic Rtl Design Engineer jobs in Fremont, CA? For Temporary Asic Rtl Design Engineer jobs in Fremont, CA, the most frequently searched job titles are:
What job categories do people searching Temporary Asic Rtl Design Engineer jobs in Fremont, CA look for? The top searched job categories for Temporary Asic Rtl Design Engineer jobs in Fremont, CA are:
What cities near Fremont, CA are hiring for Temporary Asic Rtl Design Engineer jobs? Cities near Fremont, CA with the most Temporary Asic Rtl Design Engineer job openings:
Temporary Asic Rtl Design Engineer jobs near you
Infographic showing various Temporary Asic Rtl Design Engineer job openings in Fremont, CA as of July 2026, with employment types broken down into 21% As Needed, 73% Full Time, 2% Part Time, 3% Contract, and 1% Summer. Highlights an 87% Physical, 8% Hybrid, and 5% Remote job distribution, with an average salary of $164,414 per year, or $79 per hour.

RTL Engineer Networking ASIC Saratoga, CA Full-Time

VortexLink

Saratoga, CA • On-site

Other

Re-posted 7 days ago

Job description

RTL Engineer – Networking ASIC

Saratoga, CA
Full-Time

Join an innovative hardware company building next-generation Networking ASICs that power large-scale AI training and inference.

We are seeking experienced RTL Engineers to architect and implement high-performance networking chips focused on low latency, QoS, and scalability.

Responsibilities

  • Design packet buffering, queuing, and scheduling microarchitecture

  • Implement high-speed networking ASIC RTL (SystemVerilog/Verilog)

  • Optimize pipelined architectures for performance and latency

  • Support Ethernet, IP protocols, and high-speed interconnects (e.g., UCIe)

  • Collaborate with verification teams for testing and validation

Qualifications

  • BE/ME with 8–15 years of ASIC RTL design experience

  • Strong expertise in SystemVerilog & Verilog

  • Experience with scheduling, arbitration & QoS mechanisms

  • Solid understanding of ASIC design flow (simulation, synthesis, timing)

  • Background in Ethernet and IP networking protocols

If you’re passionate about building high-speed networking silicon for AI infrastructure, apply today.

Apply