... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
ASIC Design Engineer Responsibilities: * Define and bring up FPGA platforms for pre-silicon ... Map ASIC RTL to FGPA while minimizing code base differences * Create and execute test plans for ...
Quick apply
ASIC Design Engineer Responsibilities: * Define and bring up FPGA platforms for pre-silicon ... Map ASIC RTL to FGPA while minimizing code base differences * Create and execute test plans for ...
Description As an ASIC Design Engineer on the Silicon Security team, you will be responsible for the micro-architecture, RTL design and integration of secure subsystems. Your responsibilities will ...
Description As an ASIC Design Engineer on the Silicon Security team, you will be responsible for the micro-architecture, RTL design and integration of secure subsystems. Your responsibilities will ...
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. * 4 years of experience in ASIC RTL design, with a focus on ...
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. * 4 years of experience in ASIC RTL design, with a focus on ...
Description As an ASIC Design Engineer on the Silicon Security team, you will be responsible for the micro-architecture, RTL design and integration of secure subsystems. Your responsibilities will ...
Description As an ASIC Design Engineer on the Silicon Security team, you will be responsible for the micro-architecture, RTL design and integration of secure subsystems. Your responsibilities will ...
Description As an ASIC Design Engineer on the Silicon Security team, you will be responsible for the micro-architecture, RTL design and integration of secure subsystems. Your responsibilities will ...
Description As an ASIC Design Engineer on the Silicon Security team, you will be responsible for the micro-architecture, RTL design and integration of secure subsystems. Your responsibilities will ...
RTL Design Engineer
$2.0K/mo
RTL Design Engineer As an RTL Engineer at Etched, you will be critical in ensuring that our AI ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
RTL Design Engineer
$2.0K/mo
RTL Design Engineer As an RTL Engineer at Etched, you will be critical in ensuring that our AI ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
TPU RTL Design Engineer
Sunnyvale, CA · On-site
$159K/yr
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. * 2 years of experience in ASIC RTL design, with a focus on ...
TPU RTL Design Engineer
Sunnyvale, CA · On-site
$159K/yr
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. * 2 years of experience in ASIC RTL design, with a focus on ...
ASIC / VLSI Engineers
Milpitas, CA · On-site
ASIC / VLSI ENGINEERS - RTL / STA / PD / DV (Senior Level) We are hiring 4 experienced ASIC / VLSI ... RTL Engineer (Networking / Ethernet) * STA Engineer * Physical Design Engineer * Design ...
Quick apply
ASIC / VLSI Engineers
Milpitas, CA · On-site
ASIC / VLSI ENGINEERS - RTL / STA / PD / DV (Senior Level) We are hiring 4 experienced ASIC / VLSI ... RTL Engineer (Networking / Ethernet) * STA Engineer * Physical Design Engineer * Design ...
ASIC Design Engineer - Networking/ DPU/ AI Systems
Santa Clara, CA · On-site
$180 - $240/hr
We are seeking a Senior ASIC Design Engineer with seasoned experience in the development of high ... Microarchitecture and RTL design * Design reviews * Implementation support * Tapeout * Silicon ...
ASIC Design Engineer - Networking/ DPU/ AI Systems
Santa Clara, CA · On-site
$180 - $240/hr
We are seeking a Senior ASIC Design Engineer with seasoned experience in the development of high ... Microarchitecture and RTL design * Design reviews * Implementation support * Tapeout * Silicon ...
RTL Design Engineer
Cupertino, CA · On-site
$2.0K/mo
RTL Design Engineer As an RTL Engineer at Etched, you will be critical in ensuring that our AI ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
RTL Design Engineer
Cupertino, CA · On-site
$2.0K/mo
RTL Design Engineer As an RTL Engineer at Etched, you will be critical in ensuring that our AI ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
We are seeking a Senior ASIC Design Engineer with seasoned experience in the development of high ... The ideal candidate has hands-on experience across the full ASIC development cycle -- from RTL ...
We are seeking a Senior ASIC Design Engineer with seasoned experience in the development of high ... The ideal candidate has hands-on experience across the full ASIC development cycle -- from RTL ...
Be an integral part of the System ASIC Design team to help develop and improve our RTL and SOC designs * Collaborate with architects, ASIC designers, and verification engineers to design ...
Be an integral part of the System ASIC Design team to help develop and improve our RTL and SOC designs * Collaborate with architects, ASIC designers, and verification engineers to design ...
Be an integral part of the System ASIC Design team to help develop and improve our RTL and SOC designs * Collaborate with architects, ASIC designers, and verification engineers to design ...
Be an integral part of the System ASIC Design team to help develop and improve our RTL and SOC designs * Collaborate with architects, ASIC designers, and verification engineers to design ...
ASIC Design Engineer - Networking/ DPU/ AI Systems
Santa Clara, CA · On-site
$175K/yr
The ideal candidate has hands-on experience across the full ASIC development cycle - from RTL ... We are seeking a Senior ASIC Design Engineer with seasonedexperience in the development of high ...
ASIC Design Engineer - Networking/ DPU/ AI Systems
Santa Clara, CA · On-site
$175K/yr
The ideal candidate has hands-on experience across the full ASIC development cycle - from RTL ... We are seeking a Senior ASIC Design Engineer with seasonedexperience in the development of high ...
RTL Design Engineer
San Jose, CA · On-site
$150K - $275K/yr
Job Summary As an RTL Engineer at Etched, you will be critical in ensuring that our AI chips ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
RTL Design Engineer
San Jose, CA · On-site
$150K - $275K/yr
Job Summary As an RTL Engineer at Etched, you will be critical in ensuring that our AI chips ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
Power Engineer (RTL Design)
Sunnyvale, CA · On-site
ASIC/SOC power engineers with experience on tools like PTPX / RTL-A. * We are seeking a highly skilled and motivated Contract Worker for RTL Design and Verification with expertise in power profiling ...
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Power Engineer (RTL Design)
Sunnyvale, CA · On-site
ASIC/SOC power engineers with experience on tools like PTPX / RTL-A. * We are seeking a highly skilled and motivated Contract Worker for RTL Design and Verification with expertise in power profiling ...
RTL Design Engineer
San Jose, CA · On-site
$150K - $275K/yr
Job Summary As an RTL Engineer at Etched, you will be critical in ensuring that our AI chips ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
Quick apply
RTL Design Engineer
San Jose, CA · On-site
$150K - $275K/yr
Job Summary As an RTL Engineer at Etched, you will be critical in ensuring that our AI chips ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
Description As an ASIC Design Engineer on the Silicon Security team, you will be responsible for the micro-architecture, RTL design and integration of secure subsystems. Your responsibilities will ...
Description As an ASIC Design Engineer on the Silicon Security team, you will be responsible for the micro-architecture, RTL design and integration of secure subsystems. Your responsibilities will ...
RTL Design Engineer
Palo Alto, CA · On-site
$120K - $225K/yr
We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.
RTL Design Engineer
Palo Alto, CA · On-site
$120K - $225K/yr
We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.
Temporary Asic Rtl Design Engineer information
See Fremont, CA salary details
$102.9K - $113.6K
16% of jobs
$113.6K - $124.4K
3% of jobs
$124.4K - $135.1K
4% of jobs
$138.3K is the 25th percentile. Wages below this are outliers.
$135.1K - $145.9K
6% of jobs
The median wage is $152.6K / yr.
$145.9K - $156.6K
33% of jobs
$156.6K - $167.4K
3% of jobs
$167.4K - $178.1K
2% of jobs
$185.2K is the 75th percentile. Wages above this are outliers.
$178.1K - $188.9K
12% of jobs
$188.9K - $199.6K
5% of jobs
$199.6K - $210.4K
4% of jobs
$210.4K - $221.1K
12% of jobs
$102.9K
$164.4K
$221.1K
How much do temporary asic rtl design engineer jobs pay per year?
As of Aug 23, 2026, the average yearly pay for temporary asic rtl design engineer in Fremont, CA is $164,414.00, according to ZipRecruiter salary data. Most workers in this role earn between $143,900.00 and $197,000.00 per year, depending on experience, location, and employer.
What is the difference between Temporary Asic Rtl Design Engineer vs Temporary FPGA Design Engineer?
| Aspect | Temporary Asic Rtl Design Engineer | Temporary FPGA Design Engineer |
|---|---|---|
| Primary Focus | Designing RTL code for ASIC chips | Designing FPGA logic and configurations |
| Skills & Certifications | Verilog/VHDL, ASIC design flow, simulation tools | Verilog/VHDL, FPGA development tools, synthesis |
| Work Environment | Semiconductor companies, ASIC design teams | FPGA development labs, prototyping environments |
| Industry Usage | Used in high-volume chip manufacturing | Used for prototyping, testing, and low-volume products |
Both roles involve RTL design using Verilog or VHDL, but the Temporary Asic Rtl Design Engineer focuses on ASIC chip development, while the Temporary FPGA Design Engineer specializes in FPGA-based prototyping and testing. The choice depends on whether the project aims for mass production or flexible, rapid development.
What are popular job titles related to Temporary Asic Rtl Design Engineer jobs in Fremont, CA?
For Temporary Asic Rtl Design Engineer jobs in Fremont, CA, the most frequently searched job titles are:
What job categories do people searching Temporary Asic Rtl Design Engineer jobs in Fremont, CA look for?
The top searched job categories for Temporary Asic Rtl Design Engineer jobs in Fremont, CA are:
What cities near Fremont, CA are hiring for Temporary Asic Rtl Design Engineer jobs?
Cities near Fremont, CA with the most Temporary Asic Rtl Design Engineer job openings:
Apple rating
8.0
Based on 677 frontline employees who took The Breakroom Quiz
7th of 30 rated technology retailers
Job description
Do you love creating sophisticated solutions to highly complex challenges? As part of our Hardware Technologies group, you'll help design our next-generation, high-performance, power-efficient system-on-chips (SoCs). You will ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions! Joining this group means you'll be responsible for crafting and building the technology that fuels Apple's devices. Together, we will enable our customers to do all the things they love with their devices!
In this highly visible role, you will be at the center of the Pixel IP design effort in pixel processing. You will collaborate with all teams, making a critical impact getting functional products to millions of customers quickly.
Description
As a Pixel IP DMA Design Engineer in the Pixel IP team, you will work closely with architecture, design, and verification teams to build high performance and low power DMA engines that coordinate moving large amounts of data between the memory system and the Pixel IP Engine.
In this front-end design role, your tasks will include:
- Exploring solutions to enhance performance while minimizing power and area
- Detailing specifications and building RTL designs
- Working with design verification and formal verification teams to verify functionality and performance
Minimum Qualifications
Bachelors Degree + 0 years of experience
Preferred Qualifications
Experience in multimedia IP/SoC front-end ASIC RTL design
Tight-knit collaboration skills with excellent written and verbal communication skills
Experience working multi-functionally with architecture, design, and verification teams to specify, design, and debug designs
Previous experience designing dedication DMA engines (especially related to machine learning applications), data storage, memory controllers, networking, image processing, and/or interconnects
Good understanding of arbitration, address translation, caching, on-chip interconnects, and performance analysis
Familiarity with common on-chip bus protocols such as AMBA (AXI, AHB, APB)
Experience in front-end implementation tasks such as synthesis, area and power analysis, linting, and logic equivalence checks
In this highly visible role, you will be at the center of the Pixel IP design effort in pixel processing. You will collaborate with all teams, making a critical impact getting functional products to millions of customers quickly.
Description
As a Pixel IP DMA Design Engineer in the Pixel IP team, you will work closely with architecture, design, and verification teams to build high performance and low power DMA engines that coordinate moving large amounts of data between the memory system and the Pixel IP Engine.
In this front-end design role, your tasks will include:
- Exploring solutions to enhance performance while minimizing power and area
- Detailing specifications and building RTL designs
- Working with design verification and formal verification teams to verify functionality and performance
Minimum Qualifications
Bachelors Degree + 0 years of experience
Preferred Qualifications
Experience in multimedia IP/SoC front-end ASIC RTL design
Tight-knit collaboration skills with excellent written and verbal communication skills
Experience working multi-functionally with architecture, design, and verification teams to specify, design, and debug designs
Previous experience designing dedication DMA engines (especially related to machine learning applications), data storage, memory controllers, networking, image processing, and/or interconnects
Good understanding of arbitration, address translation, caching, on-chip interconnects, and performance analysis
Familiarity with common on-chip bus protocols such as AMBA (AXI, AHB, APB)
Experience in front-end implementation tasks such as synthesis, area and power analysis, linting, and logic equivalence checks
About Apple
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Cupertino, CA, US
Year founded
1976