ASIC Design Engineer - Pixel IP DMA
$150K - $277K/yr
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
ASIC Design Engineer - Pixel IP DMA
$150K - $277K/yr
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
... Electrical Engineering or related field * 5 10 years of experience in RTL design and ... Experience working in ASIC/SoC development environments Preferred Qualifications: * Experience in ...
... Electrical Engineering or related field * 5 10 years of experience in RTL design and ... Experience working in ASIC/SoC development environments Preferred Qualifications: * Experience in ...
ASIC Engineer
San Jose, CA · On-site
$194K/yr
ASIC Engineer Location: San Jose, CA Duration: 6 Months Minimum Required Skills ... ASIC Design, FPGA, RTL Design, Chip Architecture, ASIC, Implementation,Synthesis /Conformal ...
ASIC Engineer
San Jose, CA · On-site
$194K/yr
ASIC Engineer Location: San Jose, CA Duration: 6 Months Minimum Required Skills ... ASIC Design, FPGA, RTL Design, Chip Architecture, ASIC, Implementation,Synthesis /Conformal ...
ASIC Design Engineer - Pixel IP DMA
$129K - $194K/yr
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
ASIC Design Engineer - Pixel IP DMA
$129K - $194K/yr
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
ASIC Design Engineer - Pixel IP DMA
$184K - $324K/yr
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
ASIC Design Engineer - Pixel IP DMA
$184K - $324K/yr
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
ASIC Design Engineer - Pixel IP DMA
$150K - $277K/yr
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
ASIC Design Engineer - Pixel IP DMA
$150K - $277K/yr
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
Description As an ASIC Design Engineer on the Silicon Security team, you will be responsible for the micro-architecture, RTL design and integration of secure subsystems. Your responsibilities will ...
Description As an ASIC Design Engineer on the Silicon Security team, you will be responsible for the micro-architecture, RTL design and integration of secure subsystems. Your responsibilities will ...
RTL Design Engineer
Palo Alto, CA · On-site
$120K - $225K/yr
We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.
RTL Design Engineer
Palo Alto, CA · On-site
$120K - $225K/yr
We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.
Description As an ASIC Design Engineer on the Silicon Security team, you will be responsible for the micro-architecture, RTL design and integration of secure subsystems. Your responsibilities will ...
Description As an ASIC Design Engineer on the Silicon Security team, you will be responsible for the micro-architecture, RTL design and integration of secure subsystems. Your responsibilities will ...
NVIDIA is seeking ASIC Design Engineers to implement the world's leading SoC's and GPU's. This ... Craft micro-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean ...
NVIDIA is seeking ASIC Design Engineers to implement the world's leading SoC's and GPU's. This ... Craft micro-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean ...
ASIC Design Engineer - Pixel IP DMA
$129K - $194K/yr
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
ASIC Design Engineer - Pixel IP DMA
$129K - $194K/yr
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
RTL Design Engineer
Palo Alto, CA · On-site
$120K - $225K/yr
We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.
Quick apply
RTL Design Engineer
Palo Alto, CA · On-site
$120K - $225K/yr
We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.
Knowledge of ASIC flow, SerDes, and scripting. About the job In this role, you'll work to shape the ... As a PCIe Design Engineer, you will architect and implement SoC-level RTL for our next-generation ...
Knowledge of ASIC flow, SerDes, and scripting. About the job In this role, you'll work to shape the ... As a PCIe Design Engineer, you will architect and implement SoC-level RTL for our next-generation ...
Senior ASIC Design Engineer
Santa Clara, CA · On-site
$168 - $311/hr
NVIDIA is seeking ASIC Design Engineers to implement the world's leading SoC's and GPU's. This ... Craft micro-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean ...
Senior ASIC Design Engineer
Santa Clara, CA · On-site
$168 - $311/hr
NVIDIA is seeking ASIC Design Engineers to implement the world's leading SoC's and GPU's. This ... Craft micro-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean ...
NVIDIA is seeking ASIC Design Engineers to implement the world's leading SoC's and GPU's. This ... Craft micro-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean ...
NVIDIA is seeking ASIC Design Engineers to implement the world's leading SoC's and GPU's. This ... Craft micro-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean ...
ASIC Design Engineer New Grad
Santa Clara, CA · On-site
$100 - $189.75/hr
## ASIC Design Engineer - New College Grad 2026Applylocations: US, CA, Santa Claratime type: Full ... Craft micro-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean ...
ASIC Design Engineer New Grad
Santa Clara, CA · On-site
$100 - $189.75/hr
## ASIC Design Engineer - New College Grad 2026Applylocations: US, CA, Santa Claratime type: Full ... Craft micro-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean ...
RTL Design Engineer
Santa Clara, CA · Hybrid
Role: (RTL) Design Engineer Location: Santa Clara, CA (Hybrid negotiable) Interview: Phone/Skype We're looking for a seasoned RTL engineer with 7+ years of experience in #RTLDesign #Verilog #VLSI ...
RTL Design Engineer
Santa Clara, CA · Hybrid
Role: (RTL) Design Engineer Location: Santa Clara, CA (Hybrid negotiable) Interview: Phone/Skype We're looking for a seasoned RTL engineer with 7+ years of experience in #RTLDesign #Verilog #VLSI ...
Senior RTL Design Engineer, TPU
Sunnyvale, CA · On-site
$163 - $236/hr
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related ... of experience in ASIC design. * Experience with SystemVerilog/RTL coding. * Experience with ...
Senior RTL Design Engineer, TPU
Sunnyvale, CA · On-site
$163 - $236/hr
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related ... of experience in ASIC design. * Experience with SystemVerilog/RTL coding. * Experience with ...
RTL Design Engineer
Santa Clara, CA · On-site
Role: (RTL) Design Engineer Location: Santa Clara, CA (Hybrid negotiable) Interview: Phone/Skype We're looking for a seasoned RTL engineer with 7+ years of experience in #RTLDesign #Verilog #VLSI ...
RTL Design Engineer
Santa Clara, CA · On-site
Role: (RTL) Design Engineer Location: Santa Clara, CA (Hybrid negotiable) Interview: Phone/Skype We're looking for a seasoned RTL engineer with 7+ years of experience in #RTLDesign #Verilog #VLSI ...
Sr. RTL Design Engineer (Silicon Engineering)
$175K - $280K/yr
SR. RTL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building ... ASIC/SoC system integration experience * Experience with embedded CPU subsystems * Experience with ...
Sr. RTL Design Engineer (Silicon Engineering)
$175K - $280K/yr
SR. RTL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building ... ASIC/SoC system integration experience * Experience with embedded CPU subsystems * Experience with ...
Temporary Asic Rtl Design Engineer information
See Fremont, CA salary details
$102.9K - $113.6K
16% of jobs
$113.6K - $124.4K
3% of jobs
$124.4K - $135.1K
4% of jobs
$138.3K is the 25th percentile. Wages below this are outliers.
$135.1K - $145.9K
6% of jobs
The median wage is $152.6K / yr.
$145.9K - $156.6K
33% of jobs
$156.6K - $167.4K
3% of jobs
$167.4K - $178.1K
2% of jobs
$185.2K is the 75th percentile. Wages above this are outliers.
$178.1K - $188.9K
12% of jobs
$188.9K - $199.6K
5% of jobs
$199.6K - $210.4K
4% of jobs
$210.4K - $221.1K
12% of jobs
$102.9K
$164.4K
$221.1K
How much do temporary asic rtl design engineer jobs pay per year?
As of Aug 23, 2026, the average yearly pay for temporary asic rtl design engineer in Fremont, CA is $164,414.00, according to ZipRecruiter salary data. Most workers in this role earn between $143,900.00 and $197,000.00 per year, depending on experience, location, and employer.
What is the difference between Temporary Asic Rtl Design Engineer vs Temporary FPGA Design Engineer?
| Aspect | Temporary Asic Rtl Design Engineer | Temporary FPGA Design Engineer |
|---|---|---|
| Primary Focus | Designing RTL code for ASIC chips | Designing FPGA logic and configurations |
| Skills & Certifications | Verilog/VHDL, ASIC design flow, simulation tools | Verilog/VHDL, FPGA development tools, synthesis |
| Work Environment | Semiconductor companies, ASIC design teams | FPGA development labs, prototyping environments |
| Industry Usage | Used in high-volume chip manufacturing | Used for prototyping, testing, and low-volume products |
Both roles involve RTL design using Verilog or VHDL, but the Temporary Asic Rtl Design Engineer focuses on ASIC chip development, while the Temporary FPGA Design Engineer specializes in FPGA-based prototyping and testing. The choice depends on whether the project aims for mass production or flexible, rapid development.
What are popular job titles related to Temporary Asic Rtl Design Engineer jobs in Fremont, CA?
For Temporary Asic Rtl Design Engineer jobs in Fremont, CA, the most frequently searched job titles are:
What job categories do people searching Temporary Asic Rtl Design Engineer jobs in Fremont, CA look for?
The top searched job categories for Temporary Asic Rtl Design Engineer jobs in Fremont, CA are:
What cities near Fremont, CA are hiring for Temporary Asic Rtl Design Engineer jobs?
Cities near Fremont, CA with the most Temporary Asic Rtl Design Engineer job openings:
$150K - $277K/yr
Full-time
Medical, Dental, Retirement
Re-posted 10 days ago
Apple rating
8.0
Based on 677 frontline employees who took The Breakroom Quiz
7th of 30 rated technology retailers
Job description
Do you love creating sophisticated solutions to highly complex challenges? As part of our Hardware Technologies group, you’ll help design our next-generation, high-performance, power-efficient system-on-chips (SoCs). You will ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions! Joining this group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, we will enable our customers to do all the things they love with their devices!
In this highly visible role, you will be at the center of the Pixel IP design effort in pixel processing. You will collaborate with all teams, making a critical impact getting functional products to millions of customers quickly.
Description
As a Pixel IP DMA Design Engineer in the Pixel IP team, you will work closely with architecture, design, and verification teams to build high performance and low power DMA engines that coordinate moving large amounts of data between the memory system and the Pixel IP Engine.
In this front-end design role, your tasks will include:
- Exploring solutions to enhance performance while minimizing power and area
- Detailing specifications and building RTL designs
- Working with design verification and formal verification teams to verify functionality and performance
Preferred Qualifications
Experience in multimedia IP/SoC front-end ASIC RTL design
Tight-knit collaboration skills with excellent written and verbal communication skills
Experience working multi-functionally with architecture, design, and verification teams to specify, design, and debug designs
Previous experience designing dedication DMA engines (especially related to machine learning applications), data storage, memory controllers, networking, image processing, and/or interconnects
Good understanding of arbitration, address translation, caching, on-chip interconnects, and performance analysis
Familiarity with common on-chip bus protocols such as AMBA (AXI, AHB, APB)
Experience in front-end implementation tasks such as synthesis, area and power analysis, linting, and logic equivalence checks
Minimum Qualifications
Bachelors Degree + 3 years of experience
Pay & Benefits
At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $150,400 and $277,600, and your base pay will depend on your skills, qualifications, experience, and location.
Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
In this highly visible role, you will be at the center of the Pixel IP design effort in pixel processing. You will collaborate with all teams, making a critical impact getting functional products to millions of customers quickly.
Description
As a Pixel IP DMA Design Engineer in the Pixel IP team, you will work closely with architecture, design, and verification teams to build high performance and low power DMA engines that coordinate moving large amounts of data between the memory system and the Pixel IP Engine.
In this front-end design role, your tasks will include:
- Exploring solutions to enhance performance while minimizing power and area
- Detailing specifications and building RTL designs
- Working with design verification and formal verification teams to verify functionality and performance
Preferred Qualifications
Experience in multimedia IP/SoC front-end ASIC RTL design
Tight-knit collaboration skills with excellent written and verbal communication skills
Experience working multi-functionally with architecture, design, and verification teams to specify, design, and debug designs
Previous experience designing dedication DMA engines (especially related to machine learning applications), data storage, memory controllers, networking, image processing, and/or interconnects
Good understanding of arbitration, address translation, caching, on-chip interconnects, and performance analysis
Familiarity with common on-chip bus protocols such as AMBA (AXI, AHB, APB)
Experience in front-end implementation tasks such as synthesis, area and power analysis, linting, and logic equivalence checks
Minimum Qualifications
Bachelors Degree + 3 years of experience
Pay & Benefits
At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $150,400 and $277,600, and your base pay will depend on your skills, qualifications, experience, and location.
Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
About Apple
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Cupertino, CA, US
Year founded
1976