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Temporary Asic Rtl Design Engineer Jobs (NOW HIRING)

ASIC RTL/SoC Design Engineer

San Jose, CA · On-site

$110K - $300K/yr

Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...

Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ...

Principal RTL Design Engineer

San Jose, CA · On-site

  • Medical

  • Dental

  • Vision

  • Life

Set the technical bar in design reviews and mentor design engineers Required qualifications * BS or MS in EE, CE, or CS with 7+ years (or equivalent) of industry experience in ASIC RTL design

New

Sr Digital Design Engineer

Boise, ID · On-site

$110 - $170/hr

  • Medical

  • Dental

  • Vision

  • PTO

Strong knowledge of ASIC front-end design flows including RTL design, functional verification ... Demonstrated ability to improve engineering productivity through process improvements, automation ...

Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ...

SR RTL DESIGN

Boise, ID · On-site

$100 - $130/hr

Job Summary At Micron Technology, we are looking for a Senior RTL Engineer to build and develop ... Hands‑on experience with ASIC low‑power design methodologies, including UPF‑based power ...

ASIC Design Engineer

San Diego, CA · On-site

$99 - $148/hr

Engineering Group, Engineering Group > ASICS Engineering General Summary:As a leading technology ... Contribute to ASIC development activities including RTL design, static timing analysis, timing ...

Engineers in this role may work on different aspects of ASIC and SoC development, including architecture, RTL design, implementation, timing analysis, design methodology, automation, and silicon ...

SrvDigital Design Engineer

Boise, ID · On-site

$120 - $180/hr

  • Medical

  • Dental

  • Vision

  • PTO

The engineer will collaborate with architecture, verification, and physical design teams to deliver ... Strong knowledge of ASIC front-end design flows including RTL design, functional verification ...

... ASIC RTL design and microarchitecture * 3+ years designing and specifying microarchitectures of high performance computing cores (CPU/GPU/NPU) * Fluency in at least one high level programming ...

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. * 4 years of experience in ASIC RTL design, with a focus on ...

Showing results 21-40

Temporary Asic Rtl Design Engineer information

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$94K

$150.2K

$202K

How much do temporary asic rtl design engineer jobs pay per year?

As of Aug 20, 2026, the average yearly pay for temporary asic rtl design engineer in the United States is $150,195.00, according to ZipRecruiter salary data. Most workers in this role earn between $131,500.00 and $180,000.00 per year, depending on experience, location, and employer.

What is the difference between Temporary Asic Rtl Design Engineer vs Temporary FPGA Design Engineer?

AspectTemporary Asic Rtl Design EngineerTemporary FPGA Design Engineer
Primary FocusDesigning RTL code for ASIC chipsDesigning FPGA logic and configurations
Skills & CertificationsVerilog/VHDL, ASIC design flow, simulation toolsVerilog/VHDL, FPGA development tools, synthesis
Work EnvironmentSemiconductor companies, ASIC design teamsFPGA development labs, prototyping environments
Industry UsageUsed in high-volume chip manufacturingUsed for prototyping, testing, and low-volume products

Both roles involve RTL design using Verilog or VHDL, but the Temporary Asic Rtl Design Engineer focuses on ASIC chip development, while the Temporary FPGA Design Engineer specializes in FPGA-based prototyping and testing. The choice depends on whether the project aims for mass production or flexible, rapid development.

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Infographic showing various Temporary Asic Rtl Design Engineer job openings in the United States as of August 2026, with employment types broken down into 89% Full Time, 7% Part Time, and 4% Contract. Highlights an 83% Physical, 5% Hybrid, and 12% Remote job distribution, with an average salary of $150,195 per year, or $72.2 per hour.

Rtl Design Engineer - 2202600

Ethan Alexander Group

Cupertino, CA

Full-time

Re-posted 10 days ago


Job description

RTL Design Engineer


Building AI chips that are hard-coded for individual model architectures.


RTL Design Engineer

As an RTL Engineer, you will be critical in ensuring that our AI chips operate correctly and efficiently. You will develop and implement design verification strategies for both our existing and upcoming ASIC designs.


In this role, you will work closely with state-of-the-art architectures for machine learning. You do not need to have experience working with these yet, but you will be willing and able to learn quickly. You will work in a fast-paced environment with a high degree of autonomy, and be responsible for a key part of the team's success.


Representative projects:

  • Implement a block to efficiently compute floating point math operators
  • Provide feedback to the uArch team to make sure blocks meet timing and area constraints


You may be a good fit if you:

  • At least 5 years of work experience in RTL development.
  • Experience with high-speed digital logic.
  • Proficiency in standard RTL design and synthesis tools
  • Familiarity with verification work and writing test benches
  • Are able to learn quickly about transformers and other aspects of modern artificial intelligence
  • Willing to start quickly


Strong candidates may also have experience with:

  • Experience with PCIe, Ethernet, or HBM technologies
  • Familiarity with transformer models and machine learning.
  • Familiarity with numerical representations and functions
  • ​Ability to program with Python or another scripting language