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Temporary Asic Rtl Design Engineer Jobs (NOW HIRING)

SambaNova

Principal RTL Design Engineer

Austin, TX · On-site

$180K - $255K/yr

B.S. in Electrical Engineering, Computer Engineering, or Computer Science * 7+ years of industry experience in ASIC RTL design * Mastery of synthesizable SystemVerilog for high-speed, high ...

SambaNova

Principal RTL Design Engineer

San Jose, CA · On-site

Set the technical bar in design reviews and mentor design engineers Required qualifications * BS or MS in EE, CE, or CS with 7+ years (or equivalent) of industry experience in ASIC RTL design

Google Inc.

RTL Design Engineer, TPU and ML

Sunnyvale, CA · On-site

$150 - $200/hr

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. * 4 years of experience in ASIC RTL design, with a focus on ...

TetraMem, Inc.

ASIC RTL/SoC Design Engineer

San Jose, CA · On-site

$110K - $300K/yr

Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...

Apple

ASIC Design and Integration Engineer

Beaverton, OR · On-site

Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ...

Micron Technology, Inc

SR RTL DESIGN

Boise, ID · On-site

$100 - $125/hr

Job Summary At Micron Technology, we are looking for a Senior RTL Engineer to build and develop ... Hands‑on experience with ASIC low‑power design methodologies, including UPF‑based power ...

Apple

ASIC Design and Integration Engineer

Beaverton, OR · On-site

Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Develop RTL using SystemVerilog and perform synthesis. Verification: Engage with simulation-based ...

Qualcomm

ASIC Design Engineer

San Diego, CA · On-site

Engineers in this role may work on different aspects of ASIC and SoC development, including architecture, RTL design, implementation, timing analysis, design methodology, automation, and silicon ...

Socket.dev

ASIC Design Engineer

San Diego, CA · On-site

$100 - $125/hr

Engineering Group, Engineering Group > ASICS Engineering General Summary:As a leading technology ... Contribute to ASIC development activities including RTL design, static timing analysis, timing ...

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Temporary Asic Rtl Design Engineer information

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How much do temporary asic rtl design engineer jobs pay per year?

As of Sep 9, 2026, the average yearly pay for temporary asic rtl design engineer in the United States is $150,195.00, according to ZipRecruiter salary data. Most workers in this role earn between $131,500.00 and $180,000.00 per year, depending on experience, location, and employer.

What is the difference between Temporary Asic Rtl Design Engineer vs Temporary FPGA Design Engineer?

AspectTemporary Asic Rtl Design EngineerTemporary FPGA Design Engineer
Primary FocusDesigning RTL code for ASIC chipsDesigning FPGA logic and configurations
Skills & CertificationsVerilog/VHDL, ASIC design flow, simulation toolsVerilog/VHDL, FPGA development tools, synthesis
Work EnvironmentSemiconductor companies, ASIC design teamsFPGA development labs, prototyping environments
Industry UsageUsed in high-volume chip manufacturingUsed for prototyping, testing, and low-volume products

Both roles involve RTL design using Verilog or VHDL, but the Temporary Asic Rtl Design Engineer focuses on ASIC chip development, while the Temporary FPGA Design Engineer specializes in FPGA-based prototyping and testing. The choice depends on whether the project aims for mass production or flexible, rapid development.

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Temporary Asic Rtl Design Engineer jobs near you
Infographic showing various Temporary Asic Rtl Design Engineer job openings in the United States as of September 2026, with employment types broken down into 1% Internship, 89% Full Time, 7% Part Time, and 3% Contract. Highlights an 81% Physical, 4% Hybrid, and 15% Remote job distribution, with an average salary of $150,195 per year, or $72.2 per hour.

Integration RTL Design Engineer

San Jose, CA • On-site

Advanced Micro Devices, Inc
Computer and Electronic Product Manufacturing • 5 - 10K employees
Learn more about Advanced Micro Devices, Incexternal

$145K/yr

Full-time

Re-posted 17 days ago

Advanced Micro Devices rating

8.6

Company rating: 8.6 out of 10

Based on 13 frontline employees who took The Breakroom Quiz

28th of 162 rated electronics manufacturers

Job description

WHAT YOU DO AT AMD CHANGES EVERYTHING
At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.
THE ROLE:
Join AMD's Silicon Design team to design and develop cutting-edge IPs for next-generation embedded products. As a Senior ASIC Design Engineer, you will own the complete RTL design lifecycle from micro-architecture specification through production silicon, working on complex IP design.
THE PERSON:
The ideal candidate is a seasoned ASIC/SOC designer with proven expertise across the entire chip development lifecycle-from RTL design through silicon bring-up. You excel in Verilog RTL coding, timing closure, and physical design awareness. With multiple production tape-outs under your belt, you bring deep technical expertise, strong ownership, and the ability to mentor junior engineers while driving projects to successful completion.
KEY RESPONSIBILITIES:
  • RTL Design & Microarchitecture: Author detailed micro-architecture specifications and own complete Verilog RTL implementation of major IP blocks, ensuring compliance with PPA (Performance, Power, Area) targets and timing requirements.
  • Full ASIC Development Lifecycle: Drive design from concept through production silicon across all phases: specification, RTL coding, lint/CDC checks, synthesis, timing analysis, verification, physical design integration, and post-silicon validation.
  • Timing Closure & Optimization: Develop and maintain timing constraints (SDC), perform static timing analysis (STA) using industry-standard tools (PrimeTime/Tempus), resolve timing violations, and collaborate with physical design to achieve timing closure.
  • SOC Integration: Integrate complex ASIC IP blocks into full-chip SOC environment, ensuring proper connectivity, clock domain crossings, and interface compliance with industry-standard protocols (AMBA AXI/AHB/APB, PCIe, CXL).
  • Design Quality & Verification: Partner with verification teams to ensure comprehensive functional coverage; implement design-for-test (DFT) and design-for-debug (DFD) features; participate in RTL quality reviews and signoff.
  • Physical Design Collaboration: Work closely with physical design engineers on floorplanning, placement constraints, clock tree synthesis, and power grid design to ensure timing convergence and manufacturing readiness.
  • Automation & Productivity: Develop Python/Perl/Tcl scripts to automate repetitive tasks, improve design quality checks, and enhance team efficiency throughout the design flow.
  • Cross-Functional Collaboration: Engage with architecture, verification, physical design, CAD, and post-silicon teams to resolve complex technical challenges and deliver high-quality silicon on schedule.

PREFERRED EXPERIENCE:
  • Proven track record with 2+ production ASIC tape-outs in senior design roles
  • Expert-level Verilog RTL coding skills with deep understanding of synthesizable RTL constructs and coding best practices
  • Hands-on experience with the complete ASIC design flow: RTL • Synthesis • STA • Physical Design • Tape-out
  • Experience writing and debugging SDC timing constraints, including multi-cycle paths, false paths, and clock domain crossing constraints
  • Experience integrating complex IP blocks into SOC designs
  • Knowledge of industry-standard on-chip interconnect protocols (AMBA AXI/AHB/APB)
  • Knowledge of ARM architecture and AMBA protocol specifications
  • Experience with low-power design techniques (clock gating, power gating, voltage scaling)
  • Proficiency in scripting languages: Python, Perl, Tcl, or Shell scripting
  • Exposure to formal verification tools for equivalence checking and property verification
  • Familiarity with AI-assisted design tools and modern EDA technologies
  • Experience mentoring junior engineers and leading design teams
  • Strong technical writing skills for design specifications and documentation
  • Excellent communication and collaboration skills in cross-functional environments

ACADEMIC QUALIFICATIONS:
  • Bachelor's or Master's degree in Electrical Engineering or Computer Engineering

LOCATION: San Jose, CA
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This role is not eligible for visa sponsorship.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here.
This posting is for an existing vacancy.

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