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Temporary Asic Rtl Design Engineer Jobs in Illinois

Tanisha Systems, Inc.

ASIC DFT Engineer

Rockford, IL · On-site

Title - Lead ASIC DFT Engineer Location - Remote (must be aligned with PST time zone) Type :- */W2 ... Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to ...

IMC

Hardware Engineer

Chicago, IL · On-site

$127K - $168K/yr

Design and implement RTL for next-generation ASIC platforms using SystemVerilog * Contribute to architecture and design discussions for performance-critical hardware systems * Develop new ...

IMC

Hardware Engineer

Chicago, IL · On-site

$127K - $167K/yr

Design and implement RTL for next-generation ASIC platforms using SystemVerilog * Contribute to architecture and design discussions for performance-critical hardware systems * Develop new ...

IMC

Hardware Engineer

Chicago, IL

$127K - $167K/yr

Design and implement RTL for next-generation ASIC platforms using SystemVerilog * Contribute to architecture and design discussions for performance-critical hardware systems * Develop new ...

Fermilab

Jr. ASIC Design Engineer

Batavia, IL · On-site

$70K - $93K/yr

We are looking for a Junior ASIC Design Engineer to lead and contribute to research activities and engineering work focused on developing custom instrumentation for extreme radiation and/or cryogenic ...

Eliyan

Digital - SerDes Digital Design Lead

Mundelein, IL

$138K/yr

... Engineering, or related fields * 12+ years of experience in digital design of high-speed SerDes, PHY, or transceiver IPs with proven tapeout experience at 112G PAM4 or higher data rates * Strong RTL ...

Stefanini

$121K - $167K/yr

Stefanini is looking for FPGA Design Engineer with Radio experience (Onsite Role) in Ottawa ... Working with 4G/5G Radios. 7+ years of experience Heavy System Verilog and RTL experience. They DO ...

Actalent

Design Engineer

Decatur, IL

$38 - $40/hr

Design Engineer - Hydraulic Systems Integration This on-site design engineering role focuses on ... If eligible, the benefits available for this temporary role may include the following: • Medical ...

Akuna Capital

Senior FPGA Engineer

Chicago, IL

$145K/yr

Develop and maintain RTL in Verilog/SystemVerilog * Write and maintain verification environments ... or ASIC digital logic design - network traffic experience a strong plus * Deep Verilog ...

Akuna Capital

Senior FPGA Engineer

Chicago, IL · On-site

$145K/yr

Develop and maintain RTL in Verilog/SystemVerilog * Write and maintain verification environments ... or ASIC digital logic design - network traffic experience a strong plus * Deep Verilog ...

Actalent

Manufacturing Design Engineer

Mossville, IL

$31.25 - $43.27/hr

Manufacturing Design Engineer The Mechanical Design Engineer plays a critical role on the ... If eligible, the benefits available for this temporary role may include the following: • Medical ...

New

Actalent

Design Engineer Creo

Chillicothe, IL

$31.25 - $43.27/hr

Design Engineer CREO The Design Engineer is a critical member of the IDS team whose mission is to ... If eligible, the benefits available for this temporary role may include the following: • Medical ...

New

Actalent

Mechanical Design Engineer

East Peoria, IL

$31.25 - $43.27/hr

Mechanical Design Engineer The Mechanical Design Engineer plays a critical role on the integrated ... If eligible, the benefits available for this temporary role may include the following: • Medical ...

New

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All JobsTemporary Asic Rtl Design Engineer JobsTemporary Asic Rtl Design Engineer Jobs in Illinois

Temporary Asic Rtl Design Engineer information

What is the difference between Temporary Asic Rtl Design Engineer vs Temporary FPGA Design Engineer?

AspectTemporary Asic Rtl Design EngineerTemporary FPGA Design Engineer
Primary FocusDesigning RTL code for ASIC chipsDesigning FPGA logic and configurations
Skills & CertificationsVerilog/VHDL, ASIC design flow, simulation toolsVerilog/VHDL, FPGA development tools, synthesis
Work EnvironmentSemiconductor companies, ASIC design teamsFPGA development labs, prototyping environments
Industry UsageUsed in high-volume chip manufacturingUsed for prototyping, testing, and low-volume products

Both roles involve RTL design using Verilog or VHDL, but the Temporary Asic Rtl Design Engineer focuses on ASIC chip development, while the Temporary FPGA Design Engineer specializes in FPGA-based prototyping and testing. The choice depends on whether the project aims for mass production or flexible, rapid development.

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Temporary Asic Rtl Design Engineer jobs near you
ASIC DFT Engineer

ASIC DFT Engineer

Tanisha Systems, Inc.

Rockford, IL • On-site

Other

Posted 14 days ago

Job description

Title - Lead ASIC DFT Engineer
Location – Remote (must be aligned with PST time zone)
Type :- */W2
Experience
10+ years of hands-on experience in ASIC Design-for-Test (DFT)
Role Summary
We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues.
The ideal candidate will have strong hands-on expertise in DFT fundamentals, fault models, test coverage, diagnosis, and debug, as well as the ability to evaluate and adopt emerging DFT methodologies and architecture schemes to improve robustness, quality, and yield.
Key Responsibilities
  • Lead DFT architecture, implementation, verification, and sign-off for complex ASIC and SoC designs.
  • Drive scan architecture, scan insertion, scan chain stitching, and scan compression workflows to achieve high coverage and robust testability.
  • Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon bring-up phases.
  • Perform DFT debug, failure analysis, root-cause investigation, and fault coverage closure for complex silicon issues.
  • Develop and validate DFT constraints, including DFT SDC, timing checks, and DFT-specific timing analysis.
  • Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to resolve integration and implementation issues.
  • Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug.
  • Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration.
  • Review RTL, synthesis, LEC, and physical design impacts on DFT implementation and test quality.
  • Act as a technical escalation point for advanced DFT and post-silicon debug issues.
  • Mentor junior and mid-level DFT engineers and promote best practices in DFT methodology and automation.
  • Develop scripts and automation using TCL, PERL, or Python to improve flow efficiency and debug productivity.
Required Skills & Qualifications
  • Strong hands-on experience in ASIC DFT with end-to-end ownership.
  • Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.
  • Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.
  • Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.
  • Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.
  • Experience with MBIST implementation and verification; SMS experience preferred.
  • Experience with scan architecture and scan chain stitching; Tessent/SSN experience preferred.
  • Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and physical design implementation.
  • Proven post-silicon debug and silicon bring-up experience.
  • Exposure to large SoC designs, hierarchical DFT flows, and multi-domain integration challenges.
  • Strong communication skills and the ability to work independently with minimal ramp-up.
Preferred Experience
  • MBIST post-silicon validation.
  • ATPG simulations and fault coverage debug.
  • DFT RTL, DFD, DFT verification, and IP-level DFT integration.
  • DFT SDC creation and DFT timing closure support.
  • Boundary scan, iJTAG, SSN, and design-for-debug methodologies.
  • TCL/PERL scripting for DFT automation, reporting, and debug.
  • Experience working across multiple ASIC technology nodes and complex product development cycles.
  • Familiarity with yield learning, diagnosis, and manufacturing test optimization.
Regards
Nirdosh Singh
Sr. Account Manager | Tanisha Systems Inc.
Phone: 732-377-3299 x 599
Email: nirdosh@tanishasystems.com
Web: www.tanishasystems.com
99 Wood Ave South, Suite # 308, Iselin, NJ 08830
LinkedIn :- https://www.linkedin.com/in/nirdosh-soami-rajput/
About Tanisha Systems, Inc.
Tanisha Systems, founded in 2002 in Massachusetts-*, is a leading provider of Custom Application Development and end-to-end IT Services to clients globally. We use a client-centric engagement model that combines local on-site and off-site resources with the cost, global expertise and quality advantages of off-shore operations. We deliver Custom Application Development, Application Modernization, Business Process Outsourcing and Professional IT Services from office locations in * and *.
Tanisha Systems services clients in Government, Banking & Financial Markets, Insurance, Healthcare, Retail & Consumer Goods, Energy & Utilities, Life Sciences, Telecom, Manufacturing and Transportation Industries around the globe. Our engagement model provides a flexible operational environment that empowers our clients with the right levels of control.
Want to read more about Tanisha Systems? Visit us at www.tanishasystems.com
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