Hardware Engineer
Chicago, IL · On-site
$127K - $167K/yr
Design and implement RTL for next-generation ASIC platforms using SystemVerilog * Contribute to architecture and design discussions for performance-critical hardware systems * Develop new ...
Chicago, IL · On-site
$127K - $167K/yr
Design and implement RTL for next-generation ASIC platforms using SystemVerilog * Contribute to architecture and design discussions for performance-critical hardware systems * Develop new ...
Chicago, IL · On-site
$127K - $167K/yr
Design and implement RTL for next-generation ASIC platforms using SystemVerilog * Contribute to architecture and design discussions for performance-critical hardware systems * Develop new ...
Chicago, IL · On-site
$127K - $168K/yr
Design and implement RTL for next-generation ASIC platforms using SystemVerilog * Contribute to architecture and design discussions for performance-critical hardware systems * Develop new ...
Chicago, IL · On-site
$127K - $168K/yr
Design and implement RTL for next-generation ASIC platforms using SystemVerilog * Contribute to architecture and design discussions for performance-critical hardware systems * Develop new ...
$127K - $167K/yr
Design and implement RTL for next-generation ASIC platforms using SystemVerilog * Contribute to architecture and design discussions for performance-critical hardware systems * Develop new ...
$127K - $167K/yr
Design and implement RTL for next-generation ASIC platforms using SystemVerilog * Contribute to architecture and design discussions for performance-critical hardware systems * Develop new ...
Batavia, IL · On-site
$70K - $93K/yr
We are looking for a Junior ASIC Design Engineer to lead and contribute to research activities and engineering work focused on developing custom instrumentation for extreme radiation and/or cryogenic ...
Batavia, IL · On-site
$70K - $93K/yr
We are looking for a Junior ASIC Design Engineer to lead and contribute to research activities and engineering work focused on developing custom instrumentation for extreme radiation and/or cryogenic ...
... ASIC design experience. * Sr. Principal FPGA Design Engineer (Level 4): Bachelors' degree in ... Proficient in FPGA design flow including items such as RTL/gate level simulation, synthesis, place ...
... ASIC design experience. * Sr. Principal FPGA Design Engineer (Level 4): Bachelors' degree in ... Proficient in FPGA design flow including items such as RTL/gate level simulation, synthesis, place ...
... ASIC design experience. * Sr. Principal FPGA Design Engineer (Level 4): Bachelors' degree in ... Proficient in FPGA design flow including items such as RTL/gate level simulation, synthesis, place ...
... ASIC design experience. * Sr. Principal FPGA Design Engineer (Level 4): Bachelors' degree in ... Proficient in FPGA design flow including items such as RTL/gate level simulation, synthesis, place ...
... Engineering, or related fields * 12+ years of experience in digital design of high-speed SerDes, PHY, or transceiver IPs with proven tapeout experience at 112G PAM4 or higher data rates * Strong RTL ...
Quick apply
... Engineering, or related fields * 12+ years of experience in digital design of high-speed SerDes, PHY, or transceiver IPs with proven tapeout experience at 112G PAM4 or higher data rates * Strong RTL ...
$138K - $142K/yr
As an Eliyan Sr Staff / Principal Physical Design Engineer, you will be working at a fast-paced ... You will drive the development of cutting-edge ASICs from RTL to GDSII. You will work with a cross ...
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$138K - $142K/yr
As an Eliyan Sr Staff / Principal Physical Design Engineer, you will be working at a fast-paced ... You will drive the development of cutting-edge ASICs from RTL to GDSII. You will work with a cross ...
$136K - $253K/yr
Interface with Front End RTL design teams and Back End Verification teams Position Requirements/Qualifications:
$136K - $253K/yr
Interface with Front End RTL design teams and Back End Verification teams Position Requirements/Qualifications:
Cary, IL · On-site
As such we are seeking an experienced DFT engineer which role will span across the full spectrum of ... Collaborate with RTL, verification, physical design and operation teams. Qualifications: * BS with ...
Cary, IL · On-site
As such we are seeking an experienced DFT engineer which role will span across the full spectrum of ... Collaborate with RTL, verification, physical design and operation teams. Qualifications: * BS with ...
Des Plaines, IL · On-site
Advanced knowledge of structural engineering principles, temporary works design, construction methods, and applicable codes and standards. * Ability to lead design efforts and develop engineering ...
Des Plaines, IL · On-site
Advanced knowledge of structural engineering principles, temporary works design, construction methods, and applicable codes and standards. * Ability to lead design efforts and develop engineering ...
... RTL design and verification through synthesis, place-and-route, timing, power, signoff, and ... Define and report KPIs - cycle-time reduction, engineer-hours saved, iteration count, first-pass ...
... RTL design and verification through synthesis, place-and-route, timing, power, signoff, and ... Define and report KPIs - cycle-time reduction, engineer-hours saved, iteration count, first-pass ...
Mundelein, IL · On-site
ABOUT THE ROLE As a Sr Staff / Principal CAD & Design Methodology Engineer , you will be the technical architect of RTL-to-GDSII flows and digital design infrastructure for advanced SoC products. You ...
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Mundelein, IL · On-site
ABOUT THE ROLE As a Sr Staff / Principal CAD & Design Methodology Engineer , you will be the technical architect of RTL-to-GDSII flows and digital design infrastructure for advanced SoC products. You ...
$145K/yr
Develop and maintain RTL in Verilog/SystemVerilog * Write and maintain verification environments ... or ASIC digital logic design - network traffic experience a strong plus * Deep Verilog ...
$145K/yr
Develop and maintain RTL in Verilog/SystemVerilog * Write and maintain verification environments ... or ASIC digital logic design - network traffic experience a strong plus * Deep Verilog ...
Chicago, IL · On-site
$145K/yr
Develop and maintain RTL in Verilog/SystemVerilog * Write and maintain verification environments ... or ASIC digital logic design - network traffic experience a strong plus * Deep Verilog ...
Chicago, IL · On-site
$145K/yr
Develop and maintain RTL in Verilog/SystemVerilog * Write and maintain verification environments ... or ASIC digital logic design - network traffic experience a strong plus * Deep Verilog ...
$100K - $120K/yr
UP TO THREE MONTHS OF TEMPORARY HOUSING ASSISTANCE WILL BE PROVIDED Position Overview: The ... design control and field use. Qualifications: * Bachelor of Science in Engineering Degree or ...
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$100K - $120K/yr
UP TO THREE MONTHS OF TEMPORARY HOUSING ASSISTANCE WILL BE PROVIDED Position Overview: The ... design control and field use. Qualifications: * Bachelor of Science in Engineering Degree or ...
As an Eliyan Principal Physical Design Engineer, you will be working at a fast-paced early-stage ... You will drive the development of cutting-edge ASICs from RTL to GDSII. You will work with a cross ...
Quick apply
As an Eliyan Principal Physical Design Engineer, you will be working at a fast-paced early-stage ... You will drive the development of cutting-edge ASICs from RTL to GDSII. You will work with a cross ...
$100K - $120K/yr
UP TO THREE MONTHS OF TEMPORARY HOUSING ASSISTANCE WILL BE PROVIDED Position Overview: The ... design control and field use. Qualifications: * Bachelor of Science in Engineering Degree or ...
Quick apply
$100K - $120K/yr
UP TO THREE MONTHS OF TEMPORARY HOUSING ASSISTANCE WILL BE PROVIDED Position Overview: The ... design control and field use. Qualifications: * Bachelor of Science in Engineering Degree or ...
$40 - $45/hr
Mechanical Design Engineer The Mechanical Design Engineer designs and supports precision ... If eligible, the benefits available for this temporary role may include the following: • Medical ...
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$40 - $45/hr
Mechanical Design Engineer The Mechanical Design Engineer designs and supports precision ... If eligible, the benefits available for this temporary role may include the following: • Medical ...
$40 - $45/hr
Mechanical Design Engineer The Mechanical Design Engineer designs and supports precision ... If eligible, the benefits available for this temporary role may include the following: • Medical ...
Quick apply
$40 - $45/hr
Mechanical Design Engineer The Mechanical Design Engineer designs and supports precision ... If eligible, the benefits available for this temporary role may include the following: • Medical ...
$96.8K - $106.9K
16% of jobs
$106.9K - $117.1K
3% of jobs
$117.1K - $127.2K
4% of jobs
$130.1K is the 25th percentile. Wages below this are outliers.
$127.2K - $137.3K
6% of jobs
The median wage is $143.7K / yr.
$137.3K - $147.4K
33% of jobs
$147.4K - $157.5K
3% of jobs
$157.5K - $167.6K
2% of jobs
$174.3K is the 75th percentile. Wages above this are outliers.
$167.6K - $177.7K
12% of jobs
$177.7K - $187.9K
5% of jobs
$187.9K - $198K
4% of jobs
$198K - $208.1K
12% of jobs
$96.8K
$154.7K
$208.1K
| Aspect | Temporary Asic Rtl Design Engineer | Temporary FPGA Design Engineer |
|---|---|---|
| Primary Focus | Designing RTL code for ASIC chips | Designing FPGA logic and configurations |
| Skills & Certifications | Verilog/VHDL, ASIC design flow, simulation tools | Verilog/VHDL, FPGA development tools, synthesis |
| Work Environment | Semiconductor companies, ASIC design teams | FPGA development labs, prototyping environments |
| Industry Usage | Used in high-volume chip manufacturing | Used for prototyping, testing, and low-volume products |
Both roles involve RTL design using Verilog or VHDL, but the Temporary Asic Rtl Design Engineer focuses on ASIC chip development, while the Temporary FPGA Design Engineer specializes in FPGA-based prototyping and testing. The choice depends on whether the project aims for mass production or flexible, rapid development.
$127K - $167K/yr
Full-time
PTO
Posted 5 days ago
Design and implement RTL for next-generation ASIC platforms using SystemVerilog.
Develop unit tests and verification environments for RTL designs and validate functionality and performance of hardware components.
Collaborate with hardware, software, and research teams to translate requirements into scalable hardware solutions.