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Entry Level Asic Rtl Design Engineer Jobs in Chicago, IL

Fermilab

Jr. ASIC Design Engineer

Batavia, IL · On-site

$70K - $93K/yr

We are looking for a Junior ASIC Design Engineer to lead and contribute to research activities and engineering work focused on developing custom instrumentation for extreme radiation and/or cryogenic ...

SWE Solutions

Design Engineer I

Chicago, IL · On-site

$33 - $48/hr

In this entry-level role, you will collaborate with experienced engineers and designers to develop ... Stay current with advancements in civil engineering design practices, tools, and regulations.

SWE Solutions

Design Engineer I

Chicago, IL · On-site

$33 - $48/hr

Description We are seeking a motivated Civil Design Engineer I to join our team and contribute to ... In this entry-level role, you will collaborate with experienced engineers and designers to develop ...

SWE Solutions

Design Engineer I

Chicago, IL · On-site

$33 - $48/hr

We are seeking a motivated Civil Design Engineer I to join our team and contribute to the ... In this entry-level role, you will collaborate with experienced engineers and designers to develop ...

Kinectrics

Mechanical Engineer-Entry Level

Naperville, IL · On-site

$75K - $83K/yr

Entry-Level Mechanical Engineer Location Options: Naperville, IL /Atlanta, GA Known for the ... Our Design Engineering Division provides comprehensive engineering, design, analysis and consulting ...

Kinectrics

Electrical Engineer-Entry Level 1

Naperville, IL · On-site

$75K - $83K/yr

Entry Level-Electrical Engineer Location: Naperville, IL Known for the technical excellence of its ... Our Design Engineering Division provides comprehensive engineering, design, analysis and consulting ...

dbHMS

Entry Level Electrical Engineer

Chicago, IL · Hybrid

$60K - $70K/yr

Entry Level Electrical Engineer Firm Overview Do more than just build! At dbHMS, we are a ... Our Design Studio team, in our  Chicago  office is seeking an  Entry Level Electrical ...

dbHMS

Entry Level Electrical Engineer

Chicago, IL · On-site

$60K - $70K/yr

Our Design Studio team, in our Chicago office is seeking an Entry Level Electrical Engineer . This role will support the engineering of systems for a variety of projects while working closely with ...

Qube Research & Technologies

FPGA Engineer

Chicago, IL · On-site

$180K - $280K/yr

We are looking for talented hardware engineers with a track record of achievement in any domain ... Develop RTL on the latest FPGAs with modern design flows * Following through into production ...

Qube Research & Technologies

FPGA Engineer

Chicago, IL

$180K - $280K/yr

We are looking for talented hardware engineers with a track record of achievement in any domain ... Develop RTL on the latest FPGAs with modern design flows * Following through into production ...

Sargent & Lundy

Entry Level Civil Engineer

Chicago, IL · On-site

$62K - $90K/yr

... entry-level position will offer you the opportunity to utilize and expand your civil engineering ... Design storm sewer systems, roads, trackwork, water storage and wastewater disposal ponds, and ...

Trilon Group

Water Resources Engineer

Cary, IL

$80K - $109K/yr

Our Cary office is looking for an entry level Hydraulic Engineer. The Hydraulic/Stormwater Design Engineer independently applies, plans, designs, directs, organizes, executes, and recommends ...

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All JobsEntry Level Asic Rtl Design Engineer JobsEntry Level Asic Rtl Design Engineer Jobs in Chicago, IL

Entry Level Asic Rtl Design Engineer information

See Chicago, IL salary details

$96.8K

$154.7K

$208.1K

How much do entry level asic rtl design engineer jobs pay per year?

As of Jun 9, 2026, the average yearly pay for entry level asic rtl design engineer in Chicago, IL is $154,723.00, according to ZipRecruiter salary data. Most workers in this role earn between $135,500.00 and $185,400.00 per year, depending on experience, location, and employer.

What are some typical challenges faced by Entry Level ASIC RTL Design Engineers in their first year, and how can they overcome them?

Entry Level ASIC RTL Design Engineers often encounter challenges such as understanding complex design specifications, learning company-specific design flows and tools, and debugging RTL code efficiently. Collaborating closely with senior engineers and participating in code reviews can accelerate learning and help address these challenges. Additionally, taking initiative to study relevant documentation and seeking feedback regularly will help new engineers build confidence and technical competence in their role.

What does an Entry Level ASIC RTL Design Engineer do?

An Entry Level ASIC RTL (Register Transfer Level) Design Engineer is responsible for designing and developing the digital logic that forms the core of Application Specific Integrated Circuits (ASICs). They use hardware description languages like Verilog or VHDL to create and simulate circuit designs based on functional specifications. Their tasks often include coding, debugging, verification, and collaborating with senior engineers to ensure the design meets performance, power, and area requirements. This role is essential for bringing complex digital systems from concept to physical implementation in products such as processors, networking chips, and other specialized electronics.

What are the key skills and qualifications needed to thrive as an Entry Level ASIC RTL Design Engineer, and why are they important?

To thrive as an Entry Level ASIC RTL Design Engineer, you need a solid background in digital logic design, computer architecture, and proficiency in hardware description languages like Verilog or VHDL, typically supported by a degree in electrical or computer engineering. Familiarity with EDA tools such as Synopsys or Cadence, and understanding of simulation, synthesis, and verification flows are commonly required. Strong problem-solving abilities, attention to detail, and effective teamwork and communication skills help individuals excel in this role. These skills enable accurate and efficient hardware design, seamless integration with larger teams, and successful delivery of complex semiconductor products.

What is the difference between Entry Level Asic Rtl Design Engineer vs Digital Design Engineer?

AspectEntry Level Asic Rtl Design EngineerDigital Design Engineer
Required CredentialsBachelor's in Electrical Engineering or Computer Engineering; knowledge of HDL (Verilog/VHDL)Bachelor's in Electrical Engineering, Computer Engineering, or related; HDL knowledge often required
Work EnvironmentSemiconductor companies, chip design teams, hardware development labsElectronics companies, integrated circuit design teams, hardware development labs
Industry UsagePrimarily in ASIC/FPGA chip designIn digital hardware design across various sectors including consumer electronics and telecom

While both roles involve digital hardware design and HDL skills, the Entry Level Asic Rtl Design Engineer focuses specifically on ASIC chip development, whereas the Digital Design Engineer may work on a broader range of digital systems, including FPGA and other digital hardware projects.

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Entry Level Asic Rtl Design Engineer jobs near you
Jr. ASIC Design Engineer

Jr. ASIC Design Engineer

Fermilab

Batavia, IL • On-site

$70K - $93K/yr

Full-time

Medical, Dental, Vision, Life, Retirement, PTO

Posted 18 days ago

Job description

The expected hiring range for this position is:
$70,800.00-$93,200.00.
Please note that the pay range information is a general guideline only. The pay offered to a selected candidate will be determined based on factors such the scope and responsibilities of the position, qualifications of the selected candidate, business considerations, internal equity, and external market pay for comparable jobs.
About the Role:
We are looking for a Junior ASIC Design Engineer to lead and contribute to research activities and engineering work focused on developing custom instrumentation for extreme radiation and/or cryogenic environments.
What your day-to-day as a Junior ASIC Design Engineer at Fermilab will look like:
  • Performing a leading role in Analog and RF ASIC design projects, while being able to contribute individually to major design tasks.
  • Developing design specifications for ASICs based on theoretical analyses and in conjunction with application needs.
  • Designing circuit networks using schematic entry and layout tools with full custom or timing-driven layout tools in Cadence CAD/EDA or a similar environment.
  • Models circuit networks and system components in hardware-description languages (Verilog-A and Verilog/SystemVerilog).
  • Building test benches and carries out analog and/or RF circuit simulations.
  • Executing physical and functional circuit and system verification.
  • Preparing documentation and participates in test-board designs and laboratory testing.
  • Delivering presentations internally, at national and international workshops, and at the topical conferences.
  • Performing other duties as assigned by supervisor.
  • Abiding by and being responsible for performing all duties in accordance with all environmental, health and safety regulations and practices pertinent to this position.

Skills and Attributes for Success:
  • Bachelor's degree in an applicable Engineering discipline from an ABET accredited institution.

Applicable Knowledge, Skills and Abilities Required:
  • Readiness for working on challenging projects that may have tight schedules.
  • Capability of working as part of a design team in a research and development environment
  • Experience with industry-standard front-end and back-end CAD/EDA design tools, such as Cadence, Synopsys and Mentor for the IC design.
  • Familiarity with principles of instrumentation for radiation detection with solid state or gaseous detectors and usages in extreme environments, like cryogenic or radiation harsh conditions
  • Strong computer skills and competence in performing analytical engineering calculations, in drawing schematics and in documentation.

Work Arrangement:
Please note that the described work arrangement is subject to change based on business needs and is not guaranteed to be final.
  • Hybrid: is a work arrangement in which an employee as part of an ongoing regular schedule, works at an alternative worksite in the United States (e.g., an employee's residence) on some days and at the primary worksite on other days. Requires an approved hybrid work request for one or more days a week worked remotely within the United States on a routine basis.

Benefits/Perks:
Fermilab offers a competitive and comprehensive benefits program, including:
Medical, Dental, Vision and Flexible Spending Accounts
  • Paid time off
  • Life insurance
  • Short and Long-term disability insurance
  • Retirement benefits
  • Onsite day care

Why Fermilab:
Fermilab is America's premier laboratory for particle physics and accelerator research, funded by the U.S. Department of Energy. We support discovery science experiments in Illinois and locations around the world, including deep underground mines in South Dakota and Canada, mountaintops in Arizona and Chile, CERN in Europe and the South Pole.
Pre-Employment Screening:
Drug-Free Workplace & Pre-Employment Screening
Fermilab is dedicated to fostering a safe, productive and drug-free environment. An offer of employment is contingent upon the successful completion of a background check and drug screening.
HSPD-12
In accordance with Homeland Security Presidential Directive 12 (HSPD-12) new employees are required to obtain and maintain a HSPD-12 Personal Identity Verification (PIV) Credential. To obtain this credential, new employees must successfully complete and pass a federal background check investigation. This investigation includes a declaration of illegal drug activities, including use, supply, possession, or manufacture. This includes marijuana and cannabis derivatives, which are still considered illegal under federal law, regardless of state laws. Failure to obtain or maintain such government access authorization could result in the withdrawal of a job offer or future termination of employment.
Foreign Government Sponsored Activities
Fermilab employees, and certain guest researchers and contractors, are subject to particular restrictions related to participation in Foreign Government Sponsored or Affiliated Activities, as defined and detailed in United States Department of Energy Order 486.1A. Such individuals will be asked to disclose any participation for review by Fermilab's Office of General Counsel.
REAL-ID Requirement for access to Fermilab Campus
Fermilab requires all members of the public to produce a REAL-ID, or equivalent, to access the Fermilab Campus for interviews or career events. A list of acceptable forms of ID can be found here: https://get-connected.fnal.gov/wp-content/uploads/2021/09/REALID-Documents.pdf. If a candidate is selected for an interview but does not possess any of the equivalent documents, we may schedule a virtual interview.
Equal Opportunity Statement
Fermilab is an equal opportunity employer. We evaluate qualified applicants without regard to race, color, religion, sex, age, national origin, disability, veteran status, genetic information, and other legally protected categories.

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