Hardware Engineer
Chicago, IL · On-site
$127K - $168K/yr
Design and implement RTL for next-generation ASIC platforms using SystemVerilog * Contribute to architecture and design discussions for performance-critical hardware systems * Develop new ...
Hardware Engineer
Chicago, IL · On-site
$127K - $168K/yr
Design and implement RTL for next-generation ASIC platforms using SystemVerilog * Contribute to architecture and design discussions for performance-critical hardware systems * Develop new ...
Hardware Engineer
Chicago, IL · On-site
$127K - $167K/yr
Design and implement RTL for next-generation ASIC platforms using SystemVerilog * Contribute to architecture and design discussions for performance-critical hardware systems * Develop new ...
Hardware Engineer
Chicago, IL · On-site
$127K - $167K/yr
Design and implement RTL for next-generation ASIC platforms using SystemVerilog * Contribute to architecture and design discussions for performance-critical hardware systems * Develop new ...
Hardware Engineer
Chicago, IL · On-site
$127K - $167K/yr
Design and implement RTL for next-generation ASIC platforms using SystemVerilog * Contribute to architecture and design discussions for performance-critical hardware systems * Develop new ...
Hardware Engineer
Chicago, IL · On-site
$127K - $167K/yr
Design and implement RTL for next-generation ASIC platforms using SystemVerilog * Contribute to architecture and design discussions for performance-critical hardware systems * Develop new ...
Jr. ASIC Design Engineer
Batavia, IL · On-site
$70K - $93K/yr
We are looking for a Junior ASIC Design Engineer to lead and contribute to research activities and engineering work focused on developing custom instrumentation for extreme radiation and/or cryogenic ...
Jr. ASIC Design Engineer
Batavia, IL · On-site
$70K - $93K/yr
We are looking for a Junior ASIC Design Engineer to lead and contribute to research activities and engineering work focused on developing custom instrumentation for extreme radiation and/or cryogenic ...
... ASIC design experience. * Sr. Principal FPGA Design Engineer (Level 4): Bachelors' degree in ... Proficient in FPGA design flow including items such as RTL/gate level simulation, synthesis, place ...
... ASIC design experience. * Sr. Principal FPGA Design Engineer (Level 4): Bachelors' degree in ... Proficient in FPGA design flow including items such as RTL/gate level simulation, synthesis, place ...
... ASIC design experience. * Sr. Principal FPGA Design Engineer (Level 4): Bachelors' degree in ... Proficient in FPGA design flow including items such as RTL/gate level simulation, synthesis, place ...
... ASIC design experience. * Sr. Principal FPGA Design Engineer (Level 4): Bachelors' degree in ... Proficient in FPGA design flow including items such as RTL/gate level simulation, synthesis, place ...
... Engineering, or related fields * 12+ years of experience in digital design of high-speed SerDes, PHY, or transceiver IPs with proven tapeout experience at 112G PAM4 or higher data rates * Strong RTL ...
Quick apply
... Engineering, or related fields * 12+ years of experience in digital design of high-speed SerDes, PHY, or transceiver IPs with proven tapeout experience at 112G PAM4 or higher data rates * Strong RTL ...
PD - IP Lead - Sr Staff, Physical Design
Mundelein, IL · On-site
$138K - $142K/yr
As an Eliyan Sr Staff / Principal Physical Design Engineer, you will be working at a fast-paced ... You will drive the development of cutting-edge ASICs from RTL to GDSII. You will work with a cross ...
Quick apply
PD - IP Lead - Sr Staff, Physical Design
Mundelein, IL · On-site
$138K - $142K/yr
As an Eliyan Sr Staff / Principal Physical Design Engineer, you will be working at a fast-paced ... You will drive the development of cutting-edge ASICs from RTL to GDSII. You will work with a cross ...
Lead Design Engineer
Cary, IL · On-site
$104K - $136K/yr
Interface with Front End RTL design teams and Back End Verification teams Position Requirements/Qualifications:
Lead Design Engineer
Cary, IL · On-site
$104K - $136K/yr
Interface with Front End RTL design teams and Back End Verification teams Position Requirements/Qualifications:
Principal Design Engineer
Cary, IL · On-site
$136K - $253K/yr
Interface with Front End RTL design teams and Back End Verification teams Position Requirements/Qualifications:
Principal Design Engineer
Cary, IL · On-site
$136K - $253K/yr
Interface with Front End RTL design teams and Back End Verification teams Position Requirements/Qualifications:
Senior FPGA Engineer: Low-Latency SoC Focus (Chicago)
Chicago, IL · On-site
$134K - $172K/yr
The ideal candidate will have a solid background in hardware engineering, experience with RTL design, and the ability to manage projects independently through the development lifecycle. This position ...
Senior FPGA Engineer: Low-Latency SoC Focus (Chicago)
Chicago, IL · On-site
$134K - $172K/yr
The ideal candidate will have a solid background in hardware engineering, experience with RTL design, and the ability to manage projects independently through the development lifecycle. This position ...
... RTL design and verification through synthesis, place-and-route, timing, power, signoff, and ... Define and report KPIs - cycle-time reduction, engineer-hours saved, iteration count, first-pass ...
... RTL design and verification through synthesis, place-and-route, timing, power, signoff, and ... Define and report KPIs - cycle-time reduction, engineer-hours saved, iteration count, first-pass ...
PD - Sr Staff -- CAD & Design Methodology \u007C RTL-to-GDSII Flow \u007C Advanced Node Methodology
Mundelein, IL · On-site
ABOUT THE ROLE As a Sr Staff / Principal CAD & Design Methodology Engineer , you will be the technical architect of RTL-to-GDSII flows and digital design infrastructure for advanced SoC products. You ...
Quick apply
PD - Sr Staff -- CAD & Design Methodology \u007C RTL-to-GDSII Flow \u007C Advanced Node Methodology
Mundelein, IL · On-site
ABOUT THE ROLE As a Sr Staff / Principal CAD & Design Methodology Engineer , you will be the technical architect of RTL-to-GDSII flows and digital design infrastructure for advanced SoC products. You ...
As an Eliyan Principal Physical Design Engineer, you will be working at a fast-paced early-stage ... You will drive the development of cutting-edge ASICs from RTL to GDSII. You will work with a cross ...
Quick apply
As an Eliyan Principal Physical Design Engineer, you will be working at a fast-paced early-stage ... You will drive the development of cutting-edge ASICs from RTL to GDSII. You will work with a cross ...
Junior FPGA Developer
Chicago, IL · On-site
Our team spans trading, engineering, and business operations, working together to build and support ... Design, implement, and verify RTL logic in Verilog or SystemVerilog targeting ultra-low-latency ...
Junior FPGA Developer
Chicago, IL · On-site
Our team spans trading, engineering, and business operations, working together to build and support ... Design, implement, and verify RTL logic in Verilog or SystemVerilog targeting ultra-low-latency ...
Mentor engineers on protocol implementation, timing constraints, and hierarchical design ... Extremely knowledgeable on RTL-to-GDSII flows, limitations, and flexibilities to improve ...
Quick apply
Mentor engineers on protocol implementation, timing constraints, and hierarchical design ... Extremely knowledgeable on RTL-to-GDSII flows, limitations, and flexibilities to improve ...
Campus FPGA Engineer (Intern)
Chicago, IL · On-site
$250K/yr
Experience with FPGA or other hardware/systems design and development * Experience with RTL (SystemVerilog/Verilog/VHDL) * Previous internship experience in hardware or low-level software engineering
Campus FPGA Engineer (Intern)
Chicago, IL · On-site
$250K/yr
Experience with FPGA or other hardware/systems design and development * Experience with RTL (SystemVerilog/Verilog/VHDL) * Previous internship experience in hardware or low-level software engineering
Campus FPGA Engineer (Intern)
Chicago, IL · On-site
$250K/yr
Experience with FPGA or other hardware/systems design and development * Experience with RTL (SystemVerilog/Verilog/VHDL) * Previous internship experience in hardware or low-level software engineering
Campus FPGA Engineer (Intern)
Chicago, IL · On-site
$250K/yr
Experience with FPGA or other hardware/systems design and development * Experience with RTL (SystemVerilog/Verilog/VHDL) * Previous internship experience in hardware or low-level software engineering
Experience with FPGA or other hardware/systems design and development * Experience with RTL (SystemVerilog/Verilog/VHDL) * Previous internship experience in hardware or low-level software engineering
Experience with FPGA or other hardware/systems design and development * Experience with RTL (SystemVerilog/Verilog/VHDL) * Previous internship experience in hardware or low-level software engineering
Experience with FPGA or other hardware/systems design and development * Experience with RTL (SystemVerilog/Verilog/VHDL) * Previous internship experience in hardware or low-level software engineering
Experience with FPGA or other hardware/systems design and development * Experience with RTL (SystemVerilog/Verilog/VHDL) * Previous internship experience in hardware or low-level software engineering
Freelance Asic Rtl Design Engineer information
See Chicago, IL salary details
$24.23 is the 25th percentile. Wages below this are outliers.
$15.35 - $26.34
31% of jobs
The median wage is $33.11 / hr.
$26.34 - $37.33
31% of jobs
$37.33 - $48.31
4% of jobs
$57.92 is the 75th percentile. Wages above this are outliers.
$48.31 - $59.30
10% of jobs
$59.30 - $70.28
9% of jobs
$70.28 - $81.27
5% of jobs
$81.27 - $92.25
0% of jobs
$92.25 - $103.24
8% of jobs
$103.24 - $114.23
0% of jobs
$114.23 - $125.21
0% of jobs
$125.21 - $136.20
1% of jobs
$15
$49
$136
How much do freelance asic rtl design engineer jobs pay per hour?
As of Aug 3, 2026, the average hourly pay for freelance asic rtl design engineer in Chicago, IL is $49.15, according to ZipRecruiter salary data. Most workers in this role earn between $25.00 and $63.65 per hour, depending on experience, location, and employer.
How much does a Freelance ASIC RTL Design Engineer make?
Freelance ASIC RTL Design Engineers typically earn between $50 and $150 per hour, depending on experience, project complexity, and location. Rates can vary based on expertise in hardware description languages like Verilog or VHDL and familiarity with FPGA or ASIC design tools.
Are freelance ASIC RTL design engineers in demand?
Freelance ASIC RTL design engineers are in demand due to the growing need for custom chip development in industries like telecommunications, AI, and consumer electronics. Skills in hardware description languages such as Verilog or VHDL, along with experience in FPGA prototyping, enhance employability in this competitive field.
What are the most commonly searched types of Asic Rtl Design Engineer jobs in Chicago, IL? The most popular types of Asic Rtl Design Engineer jobs in Chicago, IL are:
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Job description
IMC is seeking a Hardware Engineer to join our Global Hardware team and help develop the next generation of custom ASICs that power our trading infrastructure.
As a member of the Global Hardware organization, you'll work on long-term, high-impact engineering challenges that directly influence the performance and scalability of IMC's trading systems. This team focuses on designing proprietary hardware solutions that deliver meaningful advantages in latency-sensitive environments, partnering closely with software engineers, researchers, and trading teams to solve complex technical problems.
This role combines hardware design, verification, and system-level thinking. You'll contribute across the ASIC development lifecycle, from RTL design and validation to integration within larger hardware platforms. Because of the team's size and collaborative culture, engineers have broad ownership and exposure to multiple aspects of the design process rather than being confined to a narrow specialization.
What You'll Do
ASIC Design & Development
IMC is a global trading firm powered by a cutting-edge research environment and a world-class technology backbone. Since 1989, we've been a stabilizing force in financial markets, providing essential liquidity upon which market participants depend. Across our offices in the US, Europe, Asia Pacific, and India, our talented quant researchers, engineers, traders, and business operations professionals are united by our uniquely collaborative, high-performance culture and commitment to continuous innovation.
The Base Salary range for the role is included below. Base salary is only one component of total compensation; all full-time, permanent positions are eligible for a discretionary bonus and benefits, including paid leave and insurance. Please visit Benefits - US | IMC Trading for more comprehensive information.
The Base Salary range for the role is included below. Base salary is only one component of total compensation; all full-time, permanent positions are eligible for a discretionary bonus and benefits, including paid leave and insurance. Please visit Benefits - US | IMC Trading for more comprehensive information.
Salary Range
$200,000-$225,000 USD
About Us
IMC is a global trading firm powered by a cutting-edge research environment and a world-class technology backbone. Since 1989, we've been a stabilizing force in financial markets, providing essential liquidity upon which market participants depend. Across our offices in the US, Europe, Asia Pacific, and India, our talented quant researchers, engineers, traders, and business operations professionals are united by our uniquely collaborative, high-performance culture, and our commitment to giving back. From entering dynamic new markets to embracing disruptive technologies, and from developing an innovative research environment to diversifying our trading strategies, we dare to continuously innovate and collaborate to succeed.
As a member of the Global Hardware organization, you'll work on long-term, high-impact engineering challenges that directly influence the performance and scalability of IMC's trading systems. This team focuses on designing proprietary hardware solutions that deliver meaningful advantages in latency-sensitive environments, partnering closely with software engineers, researchers, and trading teams to solve complex technical problems.
This role combines hardware design, verification, and system-level thinking. You'll contribute across the ASIC development lifecycle, from RTL design and validation to integration within larger hardware platforms. Because of the team's size and collaborative culture, engineers have broad ownership and exposure to multiple aspects of the design process rather than being confined to a narrow specialization.
What You'll Do
ASIC Design & Development
- Participate in the full ASIC development lifecycle, from specification through integration and deployment
- Design and implement RTL for next-generation ASIC platforms using SystemVerilog
- Contribute to architecture and design discussions for performance-critical hardware systems
- Develop new functionality that supports evolving trading and infrastructure requirements
- Collaborate with hardware, software, and research teams to translate requirements into scalable solutions
- Develop unit tests and verification environments for RTL designs
- Validate functionality and performance of hardware components
- Debug design and integration issues throughout the development process
- Contribute to verification methodologies and testing infrastructure
- Ensure designs meet reliability, performance, and maintainability requirements
- Develop scripts and tooling to improve engineering workflows
- Support automation efforts across design and verification processes
- Contribute to continuous improvements in development methodologies and engineering practices
- BS+ in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline
- Strong experience with RTL design and development using SystemVerilog
- Strong understanding of digital design fundamentals
- Working knowledge of C++
- Experience developing and executing verification and test strategies
- Experience working with multi-clock-domain designs and clock-domain crossing concepts
- Solid understanding of Ethernet protocols and networking fundamentals
- Experience with Python, Bash, or similar scripting languages
- Strong debugging and problem-solving skills
- Ability to collaborate effectively across multiple engineering disciplines
- ASIC development experience
- FPGA development experience with relevant ASIC design exposure
- Familiarity with PMA (Physical Media Attachment) technologies
- Experience with high-performance networking systems
- Experience designing low-latency or performance-sensitive systems
- Exposure to trading, market infrastructure, or financial technology environments
- Experience building verification frameworks or test automation tools
- Strong C++ development skills
- Balances architecture-level thinking with hands-on implementation
- Enjoys solving difficult technical problems across hardware and software domains
- Takes ownership of systems and follows through from design to deployment
- Demonstrates strong attention to detail and engineering rigor
- Thrives in collaborative environments and works well across teams
- Learns quickly and adapts to evolving technical challenges
- Communicates clearly and effectively with both technical and non-technical stakeholders
IMC is a global trading firm powered by a cutting-edge research environment and a world-class technology backbone. Since 1989, we've been a stabilizing force in financial markets, providing essential liquidity upon which market participants depend. Across our offices in the US, Europe, Asia Pacific, and India, our talented quant researchers, engineers, traders, and business operations professionals are united by our uniquely collaborative, high-performance culture and commitment to continuous innovation.
The Base Salary range for the role is included below. Base salary is only one component of total compensation; all full-time, permanent positions are eligible for a discretionary bonus and benefits, including paid leave and insurance. Please visit Benefits - US | IMC Trading for more comprehensive information.
The Base Salary range for the role is included below. Base salary is only one component of total compensation; all full-time, permanent positions are eligible for a discretionary bonus and benefits, including paid leave and insurance. Please visit Benefits - US | IMC Trading for more comprehensive information.
Salary Range
$200,000-$225,000 USD
About Us
IMC is a global trading firm powered by a cutting-edge research environment and a world-class technology backbone. Since 1989, we've been a stabilizing force in financial markets, providing essential liquidity upon which market participants depend. Across our offices in the US, Europe, Asia Pacific, and India, our talented quant researchers, engineers, traders, and business operations professionals are united by our uniquely collaborative, high-performance culture, and our commitment to giving back. From entering dynamic new markets to embracing disruptive technologies, and from developing an innovative research environment to diversifying our trading strategies, we dare to continuously innovate and collaborate to succeed.