Hardware Engineer
Chicago, IL · On-site
$127K - $168K/yr
Design and implement RTL for next-generation ASIC platforms using SystemVerilog * Contribute to architecture and design discussions for performance-critical hardware systems * Develop new ...
Hardware Engineer
Chicago, IL · On-site
$127K - $168K/yr
Design and implement RTL for next-generation ASIC platforms using SystemVerilog * Contribute to architecture and design discussions for performance-critical hardware systems * Develop new ...
Hardware Engineer
Chicago, IL · On-site
$127K - $167K/yr
Design and implement RTL for next-generation ASIC platforms using SystemVerilog * Contribute to architecture and design discussions for performance-critical hardware systems * Develop new ...
Hardware Engineer
Chicago, IL · On-site
$127K - $167K/yr
Design and implement RTL for next-generation ASIC platforms using SystemVerilog * Contribute to architecture and design discussions for performance-critical hardware systems * Develop new ...
Hardware Engineer
Chicago, IL · On-site
$127K - $167K/yr
Design and implement RTL for next-generation ASIC platforms using SystemVerilog * Contribute to architecture and design discussions for performance-critical hardware systems * Develop new ...
Hardware Engineer
Chicago, IL · On-site
$127K - $167K/yr
Design and implement RTL for next-generation ASIC platforms using SystemVerilog * Contribute to architecture and design discussions for performance-critical hardware systems * Develop new ...
Jr. ASIC Design Engineer
Batavia, IL · On-site
$70K - $93K/yr
We are looking for a Junior ASIC Design Engineer to lead and contribute to research activities and engineering work focused on developing custom instrumentation for extreme radiation and/or cryogenic ...
Jr. ASIC Design Engineer
Batavia, IL · On-site
$70K - $93K/yr
We are looking for a Junior ASIC Design Engineer to lead and contribute to research activities and engineering work focused on developing custom instrumentation for extreme radiation and/or cryogenic ...
... ASIC design experience. * Sr. Principal FPGA Design Engineer (Level 4): Bachelors' degree in ... Proficient in FPGA design flow including items such as RTL/gate level simulation, synthesis, place ...
... ASIC design experience. * Sr. Principal FPGA Design Engineer (Level 4): Bachelors' degree in ... Proficient in FPGA design flow including items such as RTL/gate level simulation, synthesis, place ...
... ASIC design experience. * Sr. Principal FPGA Design Engineer (Level 4): Bachelors' degree in ... Proficient in FPGA design flow including items such as RTL/gate level simulation, synthesis, place ...
... ASIC design experience. * Sr. Principal FPGA Design Engineer (Level 4): Bachelors' degree in ... Proficient in FPGA design flow including items such as RTL/gate level simulation, synthesis, place ...
Digital - SerDes Digital Design Lead
Mundelein, IL · On-site
$138K/yr
... Engineering, or related fields * 12+ years of experience in digital design of high-speed SerDes, PHY, or transceiver IPs with proven tapeout experience at 112G PAM4 or higher data rates * Strong RTL ...
Quick apply
Digital - SerDes Digital Design Lead
Mundelein, IL · On-site
$138K/yr
... Engineering, or related fields * 12+ years of experience in digital design of high-speed SerDes, PHY, or transceiver IPs with proven tapeout experience at 112G PAM4 or higher data rates * Strong RTL ...
PD - IP Lead - Sr Staff, Physical Design
Mundelein, IL · On-site
$138K - $142K/yr
As an Eliyan Sr Staff / Principal Physical Design Engineer, you will be working at a fast-paced ... You will drive the development of cutting-edge ASICs from RTL to GDSII. You will work with a cross ...
Quick apply
PD - IP Lead - Sr Staff, Physical Design
Mundelein, IL · On-site
$138K - $142K/yr
As an Eliyan Sr Staff / Principal Physical Design Engineer, you will be working at a fast-paced ... You will drive the development of cutting-edge ASICs from RTL to GDSII. You will work with a cross ...
Lead Design Engineer
Cary, IL · On-site
$104K - $136K/yr
Interface with Front End RTL design teams and Back End Verification teams Position Requirements/Qualifications:
Lead Design Engineer
Cary, IL · On-site
$104K - $136K/yr
Interface with Front End RTL design teams and Back End Verification teams Position Requirements/Qualifications:
Design Engineer
$68K - $80K/yr
Design and modify components and assemblies using SolidWorks * Create detailed 2D drawings with ... Bachelor's degree in Mechanical Engineering * 0-3 years of engineering experience (internships/co ...
Quick apply
Design Engineer
$68K - $80K/yr
Design and modify components and assemblies using SolidWorks * Create detailed 2D drawings with ... Bachelor's degree in Mechanical Engineering * 0-3 years of engineering experience (internships/co ...
Principal Design Engineer
Cary, IL · On-site
$136K - $253K/yr
Interface with Front End RTL design teams and Back End Verification teams Position Requirements/Qualifications:
Principal Design Engineer
Cary, IL · On-site
$136K - $253K/yr
Interface with Front End RTL design teams and Back End Verification teams Position Requirements/Qualifications:
Senior FPGA Engineer: Low-Latency SoC Focus (Chicago)
Chicago, IL · On-site
$134K - $172K/yr
The ideal candidate will have a solid background in hardware engineering, experience with RTL design, and the ability to manage projects independently through the development lifecycle. This position ...
Senior FPGA Engineer: Low-Latency SoC Focus (Chicago)
Chicago, IL · On-site
$134K - $172K/yr
The ideal candidate will have a solid background in hardware engineering, experience with RTL design, and the ability to manage projects independently through the development lifecycle. This position ...
Design Engineer
Des Plaines, IL · On-site
$85K - $96K/yr
Bachelor's degree in mechanical engineering ... Previous product design experience (professional and/or internship). * Proficient in Creo with ...
Design Engineer
Des Plaines, IL · On-site
$85K - $96K/yr
Bachelor's degree in mechanical engineering ... Previous product design experience (professional and/or internship). * Proficient in Creo with ...
... RTL design and verification through synthesis, place-and-route, timing, power, signoff, and ... Define and report KPIs - cycle-time reduction, engineer-hours saved, iteration count, first-pass ...
... RTL design and verification through synthesis, place-and-route, timing, power, signoff, and ... Define and report KPIs - cycle-time reduction, engineer-hours saved, iteration count, first-pass ...
Design Engineer
$85K - $96K/yr
Bachelor's degree in mechanical engineering ... Previous product design experience (professional and/or internship). * Proficient in Creo with ...
Design Engineer
$85K - $96K/yr
Bachelor's degree in mechanical engineering ... Previous product design experience (professional and/or internship). * Proficient in Creo with ...
Junior FPGA Developer
Chicago, IL · On-site
Our team spans trading, engineering, and business operations, working together to build and support ... with RTL design in Verilog or SystemVerilog - coursework, personal projects, or internship ...
Junior FPGA Developer
Chicago, IL · On-site
Our team spans trading, engineering, and business operations, working together to build and support ... with RTL design in Verilog or SystemVerilog - coursework, personal projects, or internship ...
Design Engineer - Americas
Chicago, IL · Remote
$126K - $250K/yr
You have 2+ years of continuous experience (e.g., internships don't count) as an Engineer or a Designer. You have good proficiency in both Design and Engineering, with exceptional proficiency in the ...
Quick apply
Design Engineer - Americas
Chicago, IL · Remote
$126K - $250K/yr
You have 2+ years of continuous experience (e.g., internships don't count) as an Engineer or a Designer. You have good proficiency in both Design and Engineering, with exceptional proficiency in the ...
Design Engineer I
$33 - $48/hr
Internship or co-op experience in civil design or construction projects. * Knowledge of local, state, and federal engineering standards and permitting processes. * Engineer-In-Training (EIT ...
Design Engineer I
$33 - $48/hr
Internship or co-op experience in civil design or construction projects. * Knowledge of local, state, and federal engineering standards and permitting processes. * Engineer-In-Training (EIT ...
Design Engineer I
Chicago, IL · On-site
$33 - $48/hr
Internship or co-op experience in civil design or construction projects. * Knowledge of local, state, and federal engineering standards and permitting processes. * Engineer-In-Training (EIT ...
Design Engineer I
Chicago, IL · On-site
$33 - $48/hr
Internship or co-op experience in civil design or construction projects. * Knowledge of local, state, and federal engineering standards and permitting processes. * Engineer-In-Training (EIT ...
Design Engineer I
Chicago, IL · On-site
$33 - $48/hr
Internship or co-op experience in civil design or construction projects. * Knowledge of local, state, and federal engineering standards and permitting processes. * Engineer-In-Training (EIT ...
Quick apply
Design Engineer I
Chicago, IL · On-site
$33 - $48/hr
Internship or co-op experience in civil design or construction projects. * Knowledge of local, state, and federal engineering standards and permitting processes. * Engineer-In-Training (EIT ...
Internship Asic Rtl Design Engineer information
See Chicago, IL salary details
$96.8K - $106.9K
16% of jobs
$106.9K - $117.1K
3% of jobs
$117.1K - $127.2K
4% of jobs
$130.1K is the 25th percentile. Wages below this are outliers.
$127.2K - $137.3K
6% of jobs
The median wage is $143.7K / yr.
$137.3K - $147.4K
33% of jobs
$147.4K - $157.5K
3% of jobs
$157.5K - $167.6K
2% of jobs
$174.3K is the 75th percentile. Wages above this are outliers.
$167.6K - $177.7K
12% of jobs
$177.7K - $187.9K
5% of jobs
$187.9K - $198K
4% of jobs
$198K - $208.1K
12% of jobs
$96.8K
$154.7K
$208.1K
How much do internship asic rtl design engineer jobs pay per year?
As of Aug 4, 2026, the average yearly pay for internship asic rtl design engineer in Chicago, IL is $154,723.00, according to ZipRecruiter salary data. Most workers in this role earn between $135,500.00 and $185,400.00 per year, depending on experience, location, and employer.
What does an internship ASIC RTL design engineer do?
As an ASIC RTL Design Engineering intern, you'll typically work on tasks such as writing and verifying RTL code using languages like Verilog or VHDL, assisting with simulation and debugging, and collaborating closely with senior engineers on real design blocks. Interns often participate in design reviews, update documentation, and may get hands-on experience with synthesis and timing analysis tools. This role is highly collaborative and provides exposure to the complete ASIC development cycle, making it an excellent opportunity to build foundational skills and gain insight into industry-standard methodologies.
What are the key skills and qualifications needed to thrive as an internship ASIC RTL design engineer?
To thrive as an Internship ASIC RTL Design Engineer, you need a solid understanding of digital logic design, computer architecture, and proficiency in HDL languages like Verilog or VHDL, typically supported by coursework in electrical or computer engineering. Familiarity with industry-standard EDA tools such as Synopsys, Cadence, or Mentor Graphics, and simulation environments is highly valuable. Strong analytical thinking, attention to detail, and effective communication skills help interns collaborate with teams and learn quickly in a fast-paced environment. These skills and qualities are essential for contributing to complex chip design projects and ensuring accuracy and efficiency in RTL development.
What is an internship ASIC RTL design engineer?
An Internship ASIC RTL (Register Transfer Level) Design Engineer is a student or recent graduate who assists in designing and developing digital integrated circuits (ICs) using hardware description languages like Verilog or VHDL. They work under the guidance of senior engineers to create, simulate, and verify RTL code for ASIC (Application Specific Integrated Circuit) projects. The role provides hands-on experience with the chip design process, including synthesis, timing analysis, and verification. Interns gain valuable exposure to industry-standard tools and methodologies, helping them prepare for a full-time engineering career.
What is the difference between Internship Asic Rtl Design Engineer vs Asic Verification Engineer?
| Aspect | Internship Asic Rtl Design Engineer | Asic Verification Engineer |
|---|---|---|
| Credentials | Typically pursuing or recently completed a degree in Electrical Engineering or Computer Engineering | Similar educational background, often with additional coursework in verification methodologies |
| Work Environment | Internship setting, supervised, focused on learning and assisting in RTL design tasks | Full-time role, focused on testing and verifying RTL designs |
| Industry Usage | Used in semiconductor and chip design companies during early career stages | Common in companies developing complex integrated circuits and chips |
The Internship Asic Rtl Design Engineer focuses on assisting in RTL design tasks during an internship, emphasizing learning and support. In contrast, the Asic Verification Engineer is responsible for verifying RTL designs to ensure functionality. Both roles require similar educational backgrounds but differ in responsibilities and work environment, with verification roles being more advanced and permanent.
What are the most commonly searched types of Asic Rtl Design Engineer jobs in Chicago, IL? The most popular types of Asic Rtl Design Engineer jobs in Chicago, IL are:
What are popular job titles related to Internship Asic Rtl Design Engineer jobs in Chicago, IL? For Internship Asic Rtl Design Engineer jobs in Chicago, IL, the most frequently searched job titles are:
- Internship Fpga Verification Engineer
- Remote Vhdl Verilog
- Contract Asic Design Engineer
- Engineer Fpga Internship
- Junior Fpga Internships
- Remote Asic Soc Design Engineer
- Work From Home Analog Mixed Signal Design Engineer
- Freelance Asic Verification Engineer
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- Work From Home Analog Ic Design Engineer
What job categories do people searching Internship Asic Rtl Design Engineer jobs in Chicago, IL look for? The top searched job categories for Internship Asic Rtl Design Engineer jobs in Chicago, IL are:
What cities near Chicago, IL are hiring for Internship Asic Rtl Design Engineer jobs? Cities near Chicago, IL with the most Internship Asic Rtl Design Engineer job openings:
Job description
IMC is seeking a Hardware Engineer to join our Global Hardware team and help develop the next generation of custom ASICs that power our trading infrastructure.
As a member of the Global Hardware organization, you'll work on long-term, high-impact engineering challenges that directly influence the performance and scalability of IMC's trading systems. This team focuses on designing proprietary hardware solutions that deliver meaningful advantages in latency-sensitive environments, partnering closely with software engineers, researchers, and trading teams to solve complex technical problems.
This role combines hardware design, verification, and system-level thinking. You'll contribute across the ASIC development lifecycle, from RTL design and validation to integration within larger hardware platforms. Because of the team's size and collaborative culture, engineers have broad ownership and exposure to multiple aspects of the design process rather than being confined to a narrow specialization.
What You'll Do
ASIC Design & Development
IMC is a global trading firm powered by a cutting-edge research environment and a world-class technology backbone. Since 1989, we've been a stabilizing force in financial markets, providing essential liquidity upon which market participants depend. Across our offices in the US, Europe, Asia Pacific, and India, our talented quant researchers, engineers, traders, and business operations professionals are united by our uniquely collaborative, high-performance culture and commitment to continuous innovation.
The Base Salary range for the role is included below. Base salary is only one component of total compensation; all full-time, permanent positions are eligible for a discretionary bonus and benefits, including paid leave and insurance. Please visit Benefits - US | IMC Trading for more comprehensive information.
The Base Salary range for the role is included below. Base salary is only one component of total compensation; all full-time, permanent positions are eligible for a discretionary bonus and benefits, including paid leave and insurance. Please visit Benefits - US | IMC Trading for more comprehensive information.
Salary Range
$200,000-$225,000 USD
About Us
IMC is a global trading firm powered by a cutting-edge research environment and a world-class technology backbone. Since 1989, we've been a stabilizing force in financial markets, providing essential liquidity upon which market participants depend. Across our offices in the US, Europe, Asia Pacific, and India, our talented quant researchers, engineers, traders, and business operations professionals are united by our uniquely collaborative, high-performance culture, and our commitment to giving back. From entering dynamic new markets to embracing disruptive technologies, and from developing an innovative research environment to diversifying our trading strategies, we dare to continuously innovate and collaborate to succeed.
As a member of the Global Hardware organization, you'll work on long-term, high-impact engineering challenges that directly influence the performance and scalability of IMC's trading systems. This team focuses on designing proprietary hardware solutions that deliver meaningful advantages in latency-sensitive environments, partnering closely with software engineers, researchers, and trading teams to solve complex technical problems.
This role combines hardware design, verification, and system-level thinking. You'll contribute across the ASIC development lifecycle, from RTL design and validation to integration within larger hardware platforms. Because of the team's size and collaborative culture, engineers have broad ownership and exposure to multiple aspects of the design process rather than being confined to a narrow specialization.
What You'll Do
ASIC Design & Development
- Participate in the full ASIC development lifecycle, from specification through integration and deployment
- Design and implement RTL for next-generation ASIC platforms using SystemVerilog
- Contribute to architecture and design discussions for performance-critical hardware systems
- Develop new functionality that supports evolving trading and infrastructure requirements
- Collaborate with hardware, software, and research teams to translate requirements into scalable solutions
- Develop unit tests and verification environments for RTL designs
- Validate functionality and performance of hardware components
- Debug design and integration issues throughout the development process
- Contribute to verification methodologies and testing infrastructure
- Ensure designs meet reliability, performance, and maintainability requirements
- Develop scripts and tooling to improve engineering workflows
- Support automation efforts across design and verification processes
- Contribute to continuous improvements in development methodologies and engineering practices
- BS+ in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline
- Strong experience with RTL design and development using SystemVerilog
- Strong understanding of digital design fundamentals
- Working knowledge of C++
- Experience developing and executing verification and test strategies
- Experience working with multi-clock-domain designs and clock-domain crossing concepts
- Solid understanding of Ethernet protocols and networking fundamentals
- Experience with Python, Bash, or similar scripting languages
- Strong debugging and problem-solving skills
- Ability to collaborate effectively across multiple engineering disciplines
- ASIC development experience
- FPGA development experience with relevant ASIC design exposure
- Familiarity with PMA (Physical Media Attachment) technologies
- Experience with high-performance networking systems
- Experience designing low-latency or performance-sensitive systems
- Exposure to trading, market infrastructure, or financial technology environments
- Experience building verification frameworks or test automation tools
- Strong C++ development skills
- Balances architecture-level thinking with hands-on implementation
- Enjoys solving difficult technical problems across hardware and software domains
- Takes ownership of systems and follows through from design to deployment
- Demonstrates strong attention to detail and engineering rigor
- Thrives in collaborative environments and works well across teams
- Learns quickly and adapts to evolving technical challenges
- Communicates clearly and effectively with both technical and non-technical stakeholders
IMC is a global trading firm powered by a cutting-edge research environment and a world-class technology backbone. Since 1989, we've been a stabilizing force in financial markets, providing essential liquidity upon which market participants depend. Across our offices in the US, Europe, Asia Pacific, and India, our talented quant researchers, engineers, traders, and business operations professionals are united by our uniquely collaborative, high-performance culture and commitment to continuous innovation.
The Base Salary range for the role is included below. Base salary is only one component of total compensation; all full-time, permanent positions are eligible for a discretionary bonus and benefits, including paid leave and insurance. Please visit Benefits - US | IMC Trading for more comprehensive information.
The Base Salary range for the role is included below. Base salary is only one component of total compensation; all full-time, permanent positions are eligible for a discretionary bonus and benefits, including paid leave and insurance. Please visit Benefits - US | IMC Trading for more comprehensive information.
Salary Range
$200,000-$225,000 USD
About Us
IMC is a global trading firm powered by a cutting-edge research environment and a world-class technology backbone. Since 1989, we've been a stabilizing force in financial markets, providing essential liquidity upon which market participants depend. Across our offices in the US, Europe, Asia Pacific, and India, our talented quant researchers, engineers, traders, and business operations professionals are united by our uniquely collaborative, high-performance culture, and our commitment to giving back. From entering dynamic new markets to embracing disruptive technologies, and from developing an innovative research environment to diversifying our trading strategies, we dare to continuously innovate and collaborate to succeed.