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Internship Asic Rtl Design Engineer Jobs in Chicago, IL

Fermilab

Jr. ASIC Design Engineer

Batavia, IL · On-site

$70K - $93K/yr

We are looking for a Junior ASIC Design Engineer to lead and contribute to research activities and engineering work focused on developing custom instrumentation for extreme radiation and/or cryogenic ...

Futran Solutions

Physical Design Engineer

Mundelein, IL · Hybrid

$138K - $142K/yr

Physical Design Engineer (PD/PnR) Location: Bay Area / Austin (Hybrid Job Summary Seeking a ... with RTL, DFT, Power, and Signoff teams to achieve PPA targets. Required Qualifications • ...

New

Eliyan

Digital - SerDes Digital Design Lead

Mundelein, IL

$138K/yr

... Engineering, or related fields * 12+ years of experience in digital design of high-speed SerDes, PHY, or transceiver IPs with proven tapeout experience at 112G PAM4 or higher data rates * Strong RTL ...

Sterling Engineering Inc.

Design Engineer

Wood Dale, IL

$68K - $80K/yr

Design and modify components and assemblies using SolidWorks * Create detailed 2D drawings with ... Bachelor's degree in Mechanical Engineering * 0-3 years of engineering experience (internships/co ...

Wolverine Worldwide

FPGA Design Engineer

Chicago, IL · On-site

$110K - $160K/yr

Wolverine Trading is seeking an experienced FPGA design engineer to build high-speed, low latency ... ASIC designs required * No prior experience in the finance industry required Our flat ...

Ashby

Design Engineer, Americas

Chicago, IL · Remote

$122K - $220K/yr

You have 2+ years of continuous experience (e.g., internships don't count) as an Engineer or a Designer. You have good proficiency in both Design and Engineering, with exceptional proficiency in the ...

SWE Solutions

Design Engineer I

Chicago, IL

$33 - $48/hr

Internship or co-op experience in civil design or construction projects. * Knowledge of local, state, and federal engineering standards and permitting processes. * Engineer-In-Training (EIT ...

SWE Solutions

Design Engineer I

Chicago, IL · On-site

$33 - $48/hr

Internship or co-op experience in civil design or construction projects. * Knowledge of local, state, and federal engineering standards and permitting processes. * Engineer-In-Training (EIT ...

SWE Solutions

Design Engineer I

Chicago, IL · On-site

$33 - $48/hr

Internship or co-op experience in civil design or construction projects. * Knowledge of local, state, and federal engineering standards and permitting processes. * Engineer-In-Training (EIT ...

Akuna Capital

Senior FPGA Engineer

Chicago, IL · On-site

$145K/yr

Develop and maintain RTL in Verilog/SystemVerilog * Write and maintain verification environments ... or ASIC digital logic design - network traffic experience a strong plus * Deep Verilog ...

Akuna Capital

Senior FPGA Engineer

Chicago, IL · On-site

$145K/yr

Develop and maintain RTL in Verilog/SystemVerilog * Write and maintain verification environments ... or ASIC digital logic design - network traffic experience a strong plus * Deep Verilog ...

Eliyan

PD - Principal, Physical Design

Mundelein, IL · On-site

As an Eliyan Principal Physical Design Engineer, you will be working at a fast-paced early-stage ... You will drive the development of cutting-edge ASICs from RTL to GDSII. You will work with a cross ...

Eliyan

PD - Principal, Physical Design

Mundelein, IL

As an Eliyan Principal Physical Design Engineer, you will be working at a fast-paced early-stage ... You will drive the development of cutting-edge ASICs from RTL to GDSII. You will work with a cross ...

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Showing results 1-20

All JobsAsic Rtl Design Engineer JobsInternship Asic Rtl Design Engineer JobsInternship Asic Rtl Design Engineer Jobs in Chicago, IL

Internship Asic Rtl Design Engineer information

See Chicago, IL salary details

$96.8K

$154.7K

$208.1K

How much do internship asic rtl design engineer jobs pay per year?

As of Jun 15, 2026, the average yearly pay for internship asic rtl design engineer in Chicago, IL is $154,723.00, according to ZipRecruiter salary data. Most workers in this role earn between $135,500.00 and $185,400.00 per year, depending on experience, location, and employer.

What types of projects and responsibilities can an intern expect as an ASIC RTL Design Engineer?

As an ASIC RTL Design Engineering intern, you'll typically work on tasks such as writing and verifying RTL code using languages like Verilog or VHDL, assisting with simulation and debugging, and collaborating closely with senior engineers on real design blocks. Interns often participate in design reviews, update documentation, and may get hands-on experience with synthesis and timing analysis tools. This role is highly collaborative and provides exposure to the complete ASIC development cycle, making it an excellent opportunity to build foundational skills and gain insight into industry-standard methodologies.

What are the key skills and qualifications needed to thrive as an Internship ASIC RTL Design Engineer, and why are they important?

To thrive as an Internship ASIC RTL Design Engineer, you need a solid understanding of digital logic design, computer architecture, and proficiency in HDL languages like Verilog or VHDL, typically supported by coursework in electrical or computer engineering. Familiarity with industry-standard EDA tools such as Synopsys, Cadence, or Mentor Graphics, and simulation environments is highly valuable. Strong analytical thinking, attention to detail, and effective communication skills help interns collaborate with teams and learn quickly in a fast-paced environment. These skills and qualities are essential for contributing to complex chip design projects and ensuring accuracy and efficiency in RTL development.

What is an Internship ASIC RTL Design Engineer?

An Internship ASIC RTL (Register Transfer Level) Design Engineer is a student or recent graduate who assists in designing and developing digital integrated circuits (ICs) using hardware description languages like Verilog or VHDL. They work under the guidance of senior engineers to create, simulate, and verify RTL code for ASIC (Application Specific Integrated Circuit) projects. The role provides hands-on experience with the chip design process, including synthesis, timing analysis, and verification. Interns gain valuable exposure to industry-standard tools and methodologies, helping them prepare for a full-time engineering career.

What is the career path for ASIC design engineer?

The career path for an ASIC RTL design engineer typically starts with a bachelor's degree in electrical engineering or computer engineering, progressing to roles such as junior or senior RTL designer, then to lead or architect positions. Advancement often involves gaining experience in digital design, verification, and tools like HDL languages and EDA software, with opportunities to move into technical management or specialized roles like FPGA or system-on-chip (SoC) design.

What is RTL intern?

An RTL intern is a student or entry-level engineer gaining hands-on experience in Register Transfer Level (RTL) design, which involves developing and verifying digital hardware descriptions using hardware description languages like VHDL or Verilog. This internship typically includes tasks related to digital circuit design, simulation, and testing within an ASIC or FPGA development environment.

What is the salary of RTL design engineer?

The salary of an RTL design engineer typically ranges from $70,000 to $130,000 annually, depending on experience, location, and company size. Entry-level positions may start lower, while experienced engineers with specialized skills in hardware description languages like VHDL or Verilog can earn higher salaries.

What is the salary of ASIC design engineer?

The salary of an ASIC RTL Design Engineer typically ranges from $80,000 to $150,000 annually, depending on experience, location, and company size. Entry-level positions may start lower, while experienced engineers with specialized skills in hardware description languages and verification tools can earn higher salaries.

What is the difference between Internship Asic Rtl Design Engineer vs Asic Verification Engineer?

AspectInternship Asic Rtl Design EngineerAsic Verification Engineer
CredentialsTypically pursuing or recently completed a degree in Electrical Engineering or Computer EngineeringSimilar educational background, often with additional coursework in verification methodologies
Work EnvironmentInternship setting, supervised, focused on learning and assisting in RTL design tasksFull-time role, focused on testing and verifying RTL designs
Industry UsageUsed in semiconductor and chip design companies during early career stagesCommon in companies developing complex integrated circuits and chips

The Internship Asic Rtl Design Engineer focuses on assisting in RTL design tasks during an internship, emphasizing learning and support. In contrast, the Asic Verification Engineer is responsible for verifying RTL designs to ensure functionality. Both roles require similar educational backgrounds but differ in responsibilities and work environment, with verification roles being more advanced and permanent.

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Internship Asic Rtl Design Engineer jobs near you
Jr. ASIC Design Engineer

Jr. ASIC Design Engineer

Fermilab

Batavia, IL • On-site

$70K - $93K/yr

Full-time

Medical, Dental, Vision, Life, Retirement, PTO

Posted 23 days ago

Job description

The expected hiring range for this position is:
$70,800.00-$93,200.00.
Please note that the pay range information is a general guideline only. The pay offered to a selected candidate will be determined based on factors such the scope and responsibilities of the position, qualifications of the selected candidate, business considerations, internal equity, and external market pay for comparable jobs.
About the Role:
We are looking for a Junior ASIC Design Engineer to lead and contribute to research activities and engineering work focused on developing custom instrumentation for extreme radiation and/or cryogenic environments.
What your day-to-day as a Junior ASIC Design Engineer at Fermilab will look like:
  • Performing a leading role in Analog and RF ASIC design projects, while being able to contribute individually to major design tasks.
  • Developing design specifications for ASICs based on theoretical analyses and in conjunction with application needs.
  • Designing circuit networks using schematic entry and layout tools with full custom or timing-driven layout tools in Cadence CAD/EDA or a similar environment.
  • Models circuit networks and system components in hardware-description languages (Verilog-A and Verilog/SystemVerilog).
  • Building test benches and carries out analog and/or RF circuit simulations.
  • Executing physical and functional circuit and system verification.
  • Preparing documentation and participates in test-board designs and laboratory testing.
  • Delivering presentations internally, at national and international workshops, and at the topical conferences.
  • Performing other duties as assigned by supervisor.
  • Abiding by and being responsible for performing all duties in accordance with all environmental, health and safety regulations and practices pertinent to this position.

Skills and Attributes for Success:
  • Bachelor's degree in an applicable Engineering discipline from an ABET accredited institution.

Applicable Knowledge, Skills and Abilities Required:
  • Readiness for working on challenging projects that may have tight schedules.
  • Capability of working as part of a design team in a research and development environment
  • Experience with industry-standard front-end and back-end CAD/EDA design tools, such as Cadence, Synopsys and Mentor for the IC design.
  • Familiarity with principles of instrumentation for radiation detection with solid state or gaseous detectors and usages in extreme environments, like cryogenic or radiation harsh conditions
  • Strong computer skills and competence in performing analytical engineering calculations, in drawing schematics and in documentation.

Work Arrangement:
Please note that the described work arrangement is subject to change based on business needs and is not guaranteed to be final.
  • Hybrid: is a work arrangement in which an employee as part of an ongoing regular schedule, works at an alternative worksite in the United States (e.g., an employee's residence) on some days and at the primary worksite on other days. Requires an approved hybrid work request for one or more days a week worked remotely within the United States on a routine basis.

Benefits/Perks:
Fermilab offers a competitive and comprehensive benefits program, including:
Medical, Dental, Vision and Flexible Spending Accounts
  • Paid time off
  • Life insurance
  • Short and Long-term disability insurance
  • Retirement benefits
  • Onsite day care

Why Fermilab:
Fermilab is America's premier laboratory for particle physics and accelerator research, funded by the U.S. Department of Energy. We support discovery science experiments in Illinois and locations around the world, including deep underground mines in South Dakota and Canada, mountaintops in Arizona and Chile, CERN in Europe and the South Pole.
Pre-Employment Screening:
Drug-Free Workplace & Pre-Employment Screening
Fermilab is dedicated to fostering a safe, productive and drug-free environment. An offer of employment is contingent upon the successful completion of a background check and drug screening.
HSPD-12
In accordance with Homeland Security Presidential Directive 12 (HSPD-12) new employees are required to obtain and maintain a HSPD-12 Personal Identity Verification (PIV) Credential. To obtain this credential, new employees must successfully complete and pass a federal background check investigation. This investigation includes a declaration of illegal drug activities, including use, supply, possession, or manufacture. This includes marijuana and cannabis derivatives, which are still considered illegal under federal law, regardless of state laws. Failure to obtain or maintain such government access authorization could result in the withdrawal of a job offer or future termination of employment.
Foreign Government Sponsored Activities
Fermilab employees, and certain guest researchers and contractors, are subject to particular restrictions related to participation in Foreign Government Sponsored or Affiliated Activities, as defined and detailed in United States Department of Energy Order 486.1A. Such individuals will be asked to disclose any participation for review by Fermilab's Office of General Counsel.
REAL-ID Requirement for access to Fermilab Campus
Fermilab requires all members of the public to produce a REAL-ID, or equivalent, to access the Fermilab Campus for interviews or career events. A list of acceptable forms of ID can be found here: https://get-connected.fnal.gov/wp-content/uploads/2021/09/REALID-Documents.pdf. If a candidate is selected for an interview but does not possess any of the equivalent documents, we may schedule a virtual interview.
Equal Opportunity Statement
Fermilab is an equal opportunity employer. We evaluate qualified applicants without regard to race, color, religion, sex, age, national origin, disability, veteran status, genetic information, and other legally protected categories.

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