Hardware Engineer
Chicago, IL ยท On-site
$127K - $168K/yr
Design and implement RTL for next-generation ASIC platforms using SystemVerilog * Contribute to architecture and design discussions for performance-critical hardware systems * Develop new ...
Chicago, IL ยท On-site
$127K - $168K/yr
Design and implement RTL for next-generation ASIC platforms using SystemVerilog * Contribute to architecture and design discussions for performance-critical hardware systems * Develop new ...
Chicago, IL ยท On-site
$127K - $168K/yr
Design and implement RTL for next-generation ASIC platforms using SystemVerilog * Contribute to architecture and design discussions for performance-critical hardware systems * Develop new ...
Chicago, IL ยท On-site
$127K - $167K/yr
Design and implement RTL for next-generation ASIC platforms using SystemVerilog * Contribute to architecture and design discussions for performance-critical hardware systems * Develop new ...
Chicago, IL ยท On-site
$127K - $167K/yr
Design and implement RTL for next-generation ASIC platforms using SystemVerilog * Contribute to architecture and design discussions for performance-critical hardware systems * Develop new ...
$127K - $167K/yr
Design and implement RTL for next-generation ASIC platforms using SystemVerilog * Contribute to architecture and design discussions for performance-critical hardware systems * Develop new ...
$127K - $167K/yr
Design and implement RTL for next-generation ASIC platforms using SystemVerilog * Contribute to architecture and design discussions for performance-critical hardware systems * Develop new ...
Batavia, IL ยท On-site
$70K - $93K/yr
We are looking for a Junior ASIC Design Engineer to lead and contribute to research activities and engineering work focused on developing custom instrumentation for extreme radiation and/or cryogenic ...
Batavia, IL ยท On-site
$70K - $93K/yr
We are looking for a Junior ASIC Design Engineer to lead and contribute to research activities and engineering work focused on developing custom instrumentation for extreme radiation and/or cryogenic ...
... ASIC design experience. * Sr. Principal FPGA Design Engineer (Level 4): Bachelors' degree in ... Proficient in FPGA design flow including items such as RTL/gate level simulation, synthesis, place ...
... ASIC design experience. * Sr. Principal FPGA Design Engineer (Level 4): Bachelors' degree in ... Proficient in FPGA design flow including items such as RTL/gate level simulation, synthesis, place ...
... ASIC design experience. * Sr. Principal FPGA Design Engineer (Level 4): Bachelors' degree in ... Proficient in FPGA design flow including items such as RTL/gate level simulation, synthesis, place ...
... ASIC design experience. * Sr. Principal FPGA Design Engineer (Level 4): Bachelors' degree in ... Proficient in FPGA design flow including items such as RTL/gate level simulation, synthesis, place ...
... Engineering, or related fields * 12+ years of experience in digital design of high-speed SerDes, PHY, or transceiver IPs with proven tapeout experience at 112G PAM4 or higher data rates * Strong RTL ...
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... Engineering, or related fields * 12+ years of experience in digital design of high-speed SerDes, PHY, or transceiver IPs with proven tapeout experience at 112G PAM4 or higher data rates * Strong RTL ...
$138K - $142K/yr
As an Eliyan Sr Staff / Principal Physical Design Engineer, you will be working at a fast-paced ... You will drive the development of cutting-edge ASICs from RTL to GDSII. You will work with a cross ...
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$138K - $142K/yr
As an Eliyan Sr Staff / Principal Physical Design Engineer, you will be working at a fast-paced ... You will drive the development of cutting-edge ASICs from RTL to GDSII. You will work with a cross ...
$104K - $136K/yr
Interface with Front End RTL design teams and Back End Verification teams Position Requirements/Qualifications:
$104K - $136K/yr
Interface with Front End RTL design teams and Back End Verification teams Position Requirements/Qualifications:
Cary, IL ยท On-site
$136K - $253K/yr
Interface with Front End RTL design teams and Back End Verification teams Position Requirements/Qualifications:
Cary, IL ยท On-site
$136K - $253K/yr
Interface with Front End RTL design teams and Back End Verification teams Position Requirements/Qualifications:
... RTL design and verification through synthesis, place-and-route, timing, power, signoff, and ... Define and report KPIs - cycle-time reduction, engineer-hours saved, iteration count, first-pass ...
... RTL design and verification through synthesis, place-and-route, timing, power, signoff, and ... Define and report KPIs - cycle-time reduction, engineer-hours saved, iteration count, first-pass ...
Mundelein, IL ยท On-site
ABOUT THE ROLE As a Sr Staff / Principal CAD & Design Methodology Engineer , you will be the technical architect of RTL-to-GDSII flows and digital design infrastructure for advanced SoC products. You ...
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Mundelein, IL ยท On-site
ABOUT THE ROLE As a Sr Staff / Principal CAD & Design Methodology Engineer , you will be the technical architect of RTL-to-GDSII flows and digital design infrastructure for advanced SoC products. You ...
$145K/yr
Develop and maintain RTL in Verilog/SystemVerilog * Write and maintain verification environments ... or ASIC digital logic design - network traffic experience a strong plus * Deep Verilog ...
$145K/yr
Develop and maintain RTL in Verilog/SystemVerilog * Write and maintain verification environments ... or ASIC digital logic design - network traffic experience a strong plus * Deep Verilog ...
Chicago, IL ยท On-site
$145K/yr
Develop and maintain RTL in Verilog/SystemVerilog * Write and maintain verification environments ... or ASIC digital logic design - network traffic experience a strong plus * Deep Verilog ...
Chicago, IL ยท On-site
$145K/yr
Develop and maintain RTL in Verilog/SystemVerilog * Write and maintain verification environments ... or ASIC digital logic design - network traffic experience a strong plus * Deep Verilog ...
As an Eliyan Principal Physical Design Engineer, you will be working at a fast-paced early-stage ... You will drive the development of cutting-edge ASICs from RTL to GDSII. You will work with a cross ...
Quick apply
As an Eliyan Principal Physical Design Engineer, you will be working at a fast-paced early-stage ... You will drive the development of cutting-edge ASICs from RTL to GDSII. You will work with a cross ...
Chicago, IL ยท On-site
Our team spans trading, engineering, and business operations, working together to build and support ... Design, implement, and verify RTL logic in Verilog or SystemVerilog targeting ultra-low-latency ...
Chicago, IL ยท On-site
Our team spans trading, engineering, and business operations, working together to build and support ... Design, implement, and verify RTL logic in Verilog or SystemVerilog targeting ultra-low-latency ...
Mundelein, IL ยท On-site
Mentor engineers on protocol implementation, timing constraints, and hierarchical design ... Extremely knowledgeable on RTL-to-GDSII flows, limitations, and flexibilities to improve ...
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Mundelein, IL ยท On-site
Mentor engineers on protocol implementation, timing constraints, and hierarchical design ... Extremely knowledgeable on RTL-to-GDSII flows, limitations, and flexibilities to improve ...
Chicago, IL ยท On-site
$250K/yr
Experience with FPGA or other hardware/systems design and development * Experience with RTL (SystemVerilog/Verilog/VHDL) * Previous internship experience in hardware or low-level software engineering
Chicago, IL ยท On-site
$250K/yr
Experience with FPGA or other hardware/systems design and development * Experience with RTL (SystemVerilog/Verilog/VHDL) * Previous internship experience in hardware or low-level software engineering
Chicago, IL ยท On-site
$250K/yr
Experience with FPGA or other hardware/systems design and development * Experience with RTL (SystemVerilog/Verilog/VHDL) * Previous internship experience in hardware or low-level software engineering
Chicago, IL ยท On-site
$250K/yr
Experience with FPGA or other hardware/systems design and development * Experience with RTL (SystemVerilog/Verilog/VHDL) * Previous internship experience in hardware or low-level software engineering
This position is 100% onsite and cannot accommodate telecommute work. You will become part of Northrop Grumman's Electrical Design & Technology group, working with other engineers to develop ...
This position is 100% onsite and cannot accommodate telecommute work. You will become part of Northrop Grumman's Electrical Design & Technology group, working with other engineers to develop ...
$96.8K - $106.9K
16% of jobs
$106.9K - $117.1K
3% of jobs
$117.1K - $127.2K
4% of jobs
$130.1K is the 25th percentile. Wages below this are outliers.
$127.2K - $137.3K
6% of jobs
The median wage is $143.7K / yr.
$137.3K - $147.4K
33% of jobs
$147.4K - $157.5K
3% of jobs
$157.5K - $167.6K
2% of jobs
$174.3K is the 75th percentile. Wages above this are outliers.
$167.6K - $177.7K
12% of jobs
$177.7K - $187.9K
5% of jobs
$187.9K - $198K
4% of jobs
$198K - $208.1K
12% of jobs
$96.8K
$154.7K
$208.1K
| Aspect | Telecommute Asic Rtl Design Engineer | Telecommute Digital IC Design Engineer |
|---|---|---|
| Credentials | Bachelor's or Master's in Electrical Engineering or Computer Engineering; experience with RTL coding | Bachelor's or Master's in Electrical Engineering or Computer Engineering; experience with digital circuit design |
| Work Environment | Remote, primarily designing RTL code for ASICs | Remote, focusing on digital IC architecture and design |
| Industry Usage | Common in semiconductor and electronics companies |
Both roles often require similar educational backgrounds and work remotely in the semiconductor industry. The main difference lies in their focus: RTL Design Engineers concentrate on writing RTL code for ASICs, while Digital IC Design Engineers work on broader digital circuit architecture. Candidates should choose based on their specific skills and career interests in digital design or RTL coding.