ASIC/RTL Design Engineer
San Jose, CA · On-site
ASIC/RTL Design Engineer Location: San Jose, CA Duration : 12 months plus JOB DUTIES: The work will expose the designer to a number of IP including ARM cores, Ethernet, DDR, DMA, PCIE, SATA ...
San Jose, CA · On-site
ASIC/RTL Design Engineer Location: San Jose, CA Duration : 12 months plus JOB DUTIES: The work will expose the designer to a number of IP including ARM cores, Ethernet, DDR, DMA, PCIE, SATA ...
San Jose, CA · On-site
ASIC/RTL Design Engineer Location: San Jose, CA Duration : 12 months plus JOB DUTIES: The work will expose the designer to a number of IP including ARM cores, Ethernet, DDR, DMA, PCIE, SATA ...
Title: ASIC RTL Design Engineer - Onsite Mandatory skills: SoC Architecture, ASIC design flow, RTL coding, debugging, verification, supporting synthesis, timing closure, ARM cores, I/O standard ...
Title: ASIC RTL Design Engineer - Onsite Mandatory skills: SoC Architecture, ASIC design flow, RTL coding, debugging, verification, supporting synthesis, timing closure, ARM cores, I/O standard ...
San Jose, CA · On-site
Our RTL Design Engineers are expected contribute in all aspects of SoC design including: Chip ... SoC Architecture;knowledge and hand-on experience from industry ASIC design flow including RTL ...
San Jose, CA · On-site
Our RTL Design Engineers are expected contribute in all aspects of SoC design including: Chip ... SoC Architecture;knowledge and hand-on experience from industry ASIC design flow including RTL ...
San Jose, CA · On-site
Our RTL Design Engineers are expected contribute in all aspects of SoC design including: Chip ... SoC Architecture; knowledge and hand-on experience from industry ASIC design flow including RTL ...
San Jose, CA · On-site
Our RTL Design Engineers are expected contribute in all aspects of SoC design including: Chip ... SoC Architecture; knowledge and hand-on experience from industry ASIC design flow including RTL ...
RTL Engineer - Networking ASIC Saratoga, CA Full-Time Join an innovative hardware company building ... Design packet buffering, queuing, and scheduling microarchitecture * Implement high-speed ...
RTL Engineer - Networking ASIC Saratoga, CA Full-Time Join an innovative hardware company building ... Design packet buffering, queuing, and scheduling microarchitecture * Implement high-speed ...
San Diego, CA · On-site
$127K - $190K/yr
Engineering Group, Engineering Group > DSP Architecture and Design General Summary: A variety of ... This position involves in-depth understanding of the ASIC design flow from RTL to GDS2 and the ...
San Diego, CA · On-site
$127K - $190K/yr
Engineering Group, Engineering Group > DSP Architecture and Design General Summary: A variety of ... This position involves in-depth understanding of the ASIC design flow from RTL to GDS2 and the ...
ASIC/SoC RTL Design Engineer Location: Palo Alto, CA (Or potentially Burlington, MA) Length of Contract: 6 months+ (Temp-to-Perm) Ideal Start: 6/1/2026 Responsibilities : Own end-to-end design of ...
ASIC/SoC RTL Design Engineer Location: Palo Alto, CA (Or potentially Burlington, MA) Length of Contract: 6 months+ (Temp-to-Perm) Ideal Start: 6/1/2026 Responsibilities : Own end-to-end design of ...
San Jose, CA · On-site
$60 - $62/hr
Hands-on experience in industry ASIC design flow including RTL coding, debugging/verification, and supporting synthesis and timing closure. * Working knowledge of Client cores and other I/O standard ...
Quick apply
San Jose, CA · On-site
$60 - $62/hr
Hands-on experience in industry ASIC design flow including RTL coding, debugging/verification, and supporting synthesis and timing closure. * Working knowledge of Client cores and other I/O standard ...
San Jose, CA · Hybrid
$200K - $300K/yr
As a Senior ASIC Front-End Design Engineer, you will be responsible for all aspects of digital SoC design , from micro-architecture specification, RTL, verification, synthesis, lint, CDC, LEC, and ...
San Jose, CA · Hybrid
$200K - $300K/yr
As a Senior ASIC Front-End Design Engineer, you will be responsible for all aspects of digital SoC design , from micro-architecture specification, RTL, verification, synthesis, lint, CDC, LEC, and ...
OR · Remote
$200K - $300K/yr
As a Senior ASIC Front-End Design Engineer, you will be responsible for all aspects of digital SoC design , from micro-architecture specification, RTL, verification, synthesis, lint, CDC, LEC, and ...
OR · Remote
$200K - $300K/yr
As a Senior ASIC Front-End Design Engineer, you will be responsible for all aspects of digital SoC design , from micro-architecture specification, RTL, verification, synthesis, lint, CDC, LEC, and ...
$60 - $62.50/hr
SoC RTL Design Engineer San Jose, CA: 100% Onsite 6 + Months $60-$62.50/HR Role: Lead advanced CMOS ... ASIC design flow experience Expert RTL coding/debugging Dexian stands at the forefront of Talent ...
$60 - $62.50/hr
SoC RTL Design Engineer San Jose, CA: 100% Onsite 6 + Months $60-$62.50/HR Role: Lead advanced CMOS ... ASIC design flow experience Expert RTL coding/debugging Dexian stands at the forefront of Talent ...
Campbell, CA · On-site
$60 - $62.50/hr
SoC RTL Design Engineer San Jose, CA: 100% Onsite 6 + Months $60-$62.50/HR Role: Lead advanced CMOS ... ASIC design flow experience Expert RTL coding/debugging Dexian stands at the forefront of Talent ...
Campbell, CA · On-site
$60 - $62.50/hr
SoC RTL Design Engineer San Jose, CA: 100% Onsite 6 + Months $60-$62.50/HR Role: Lead advanced CMOS ... ASIC design flow experience Expert RTL coding/debugging Dexian stands at the forefront of Talent ...
ASIC/RTL Design Engineer Primary Skills : RTL coding, TCL coding, Python coding, understanding of different CAD tools (synthesis, lint, CDC, RDC, PrimeTime). Location: San Jose CA Duration : 12 ...
ASIC/RTL Design Engineer Primary Skills : RTL coding, TCL coding, Python coding, understanding of different CAD tools (synthesis, lint, CDC, RDC, PrimeTime). Location: San Jose CA Duration : 12 ...
... ASIC/SoC Digital Design and RTL development. · Minimum 5+ years of hands-on experience in Verilog RTL design and development. · Strong understanding of digital design fundamentals, RTL design ...
New
... ASIC/SoC Digital Design and RTL development. · Minimum 5+ years of hands-on experience in Verilog RTL design and development. · Strong understanding of digital design fundamentals, RTL design ...
New
Beaverton, OR · On-site
Sr/ ASIC Design Engineer (5+ Years of Experience) DESCRIPTION OF POSITION/DUTIES - * Architect a ... Run LINT and CDC checks on the RTL code and fix accordingly. * Assist with synthesis and FPGA ...
Beaverton, OR · On-site
Sr/ ASIC Design Engineer (5+ Years of Experience) DESCRIPTION OF POSITION/DUTIES - * Architect a ... Run LINT and CDC checks on the RTL code and fix accordingly. * Assist with synthesis and FPGA ...
Fremont, CA · On-site
Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...
Fremont, CA · On-site
Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...
Staff RTL Engineer - Ethernet Saratoga, CA Full-Time Join a cutting-edge hardware company building ... MSEE with 8-15 years of ASIC/RTL design experience * Strong expertise in Ethernet 802.3 protocols ...
Staff RTL Engineer - Ethernet Saratoga, CA Full-Time Join a cutting-edge hardware company building ... MSEE with 8-15 years of ASIC/RTL design experience * Strong expertise in Ethernet 802.3 protocols ...
As a Senior ASIC Design Engineer, you will own the complete RTL design lifecycle from micro-architecture specification through production silicon, working on complex IP design. THE PERSON: The ideal ...
As a Senior ASIC Design Engineer, you will own the complete RTL design lifecycle from micro-architecture specification through production silicon, working on complex IP design. THE PERSON: The ideal ...
Fremont, CA · On-site
Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...
Fremont, CA · On-site
Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...
San Jose, CA · On-site
$145K/yr
As a Senior ASIC Design Engineer, you will own the complete RTL design lifecycle from micro-architecture specification through production silicon, working on complex IP design. THE PERSON: The ideal ...
San Jose, CA · On-site
$145K/yr
As a Senior ASIC Design Engineer, you will own the complete RTL design lifecycle from micro-architecture specification through production silicon, working on complex IP design. THE PERSON: The ideal ...
$94K - $103.8K
16% of jobs
$103.8K - $113.6K
3% of jobs
$113.6K - $123.5K
4% of jobs
$126.3K is the 25th percentile. Wages below this are outliers.
$123.5K - $133.3K
6% of jobs
The median wage is $139.4K / yr.
$133.3K - $143.1K
33% of jobs
$143.1K - $152.9K
3% of jobs
$152.9K - $162.7K
2% of jobs
$169.2K is the 75th percentile. Wages above this are outliers.
$162.7K - $172.5K
12% of jobs
$172.5K - $182.4K
5% of jobs
$182.4K - $192.2K
4% of jobs
$192.2K - $202K
12% of jobs
$94K
$150.2K
$202K
| Aspect | Telecommute Asic Rtl Design Engineer | Telecommute Digital IC Design Engineer |
|---|---|---|
| Credentials | Bachelor's or Master's in Electrical Engineering or Computer Engineering; experience with RTL coding | Bachelor's or Master's in Electrical Engineering or Computer Engineering; experience with digital circuit design |
| Work Environment | Remote, primarily designing RTL code for ASICs | Remote, focusing on digital IC architecture and design |
| Industry Usage | Common in semiconductor and electronics companies |
Both roles often require similar educational backgrounds and work remotely in the semiconductor industry. The main difference lies in their focus: RTL Design Engineers concentrate on writing RTL code for ASICs, while Digital IC Design Engineers work on broader digital circuit architecture. Candidates should choose based on their specific skills and career interests in digital design or RTL coding.

ASIC/RTL Design Engineer
Location: San Jose, CA
Duration : 12 months plus
JOB DUTIES:
The work will expose the designer to a number of IP including ARM cores, Ethernet, DDR, DMA, PCIE, SATA
Successful candidates will be responsible for leading, and participating in, the design of leading edge SoCs in advanced digital CMOS processes. Our RTL Design Engineers are expected contribute in all aspects of SoC design including: Chip definition, Architecture development and modeling, Development of micro-architectural specifications, Conversion of micro-architectural specifications to logic implementation, Verification, emulation, debug, synthesis, and timing closure, Interfacing with physical execution, software, and silicon bring-up teams.
EXPERIENCE AND EDUCATION:
SoC Architecture; knowledge and hand-on experience from industry ASIC design flow including RTL coding, debugging/verification, and supporting synthesis and timing closure. Working knowledge of ARM cores and other I/O standard interfaces. An ideal candidate would also exhibit: Strong communication and documentation skills, Good organizational, time management and multitasking skills, Strong initiative and discipline to follow-through, Technical leadership
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51 - 200 Employees
Milpitas, CA, US
2004