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Telecommute Asic Rtl Design Engineer Jobs in Clovis, CA

Hudson River Trading

AI Researcher

London, CA · On-site

Strong engineering skills valued, especially any of: GPU kernel development, lower-level Pytorch ... ASIC experience, HPC experience. The estimated base salary range for this position is 200,000 to ...

All JobsTelecommute Asic Rtl Design Engineer JobsTelecommute Asic Rtl Design Engineer Jobs in Clovis, CA

Telecommute Asic Rtl Design Engineer information

See Clovis, CA salary details

$93.4K

$149.2K

$200.7K

How much do telecommute asic rtl design engineer jobs pay per year?

As of Aug 29, 2026, the average yearly pay for telecommute asic rtl design engineer in Clovis, CA is $149,214.00, according to ZipRecruiter salary data. Most workers in this role earn between $130,600.00 and $178,800.00 per year, depending on experience, location, and employer.

What is a telecommute ASIC RTL design engineer?

A Telecommute ASIC RTL Design Engineer is a professional who specializes in designing digital circuits at the Register Transfer Level (RTL) for Application-Specific Integrated Circuits (ASICs), while working remotely. They use hardware description languages like Verilog or VHDL to create and verify circuit designs tailored to specific applications. Their responsibilities often include developing, simulating, and optimizing digital logic, collaborating with cross-functional teams, and ensuring that the final silicon meets design specifications. Since the role is telecommute, all work is performed from a remote location using digital communication and collaboration tools.

What are the key skills and qualifications needed to thrive as a telecommute ASIC RTL design engineer?

To thrive as a Telecommute ASIC RTL Design Engineer, you need a strong background in digital logic design, proficiency in hardware description languages like Verilog or VHDL, and typically a degree in electrical or computer engineering. Familiarity with EDA tools such as Synopsys or Cadence, as well as experience with simulation, synthesis, and debugging environments, is essential. Strong problem-solving abilities, attention to detail, and effective communication skills are crucial for collaborating remotely and ensuring design accuracy. These skills are vital to deliver complex, high-performance ASICs on schedule while working efficiently in a remote setting.

What are some common challenges faced by telecommute ASIC RTL design engineers, and how can they be addressed?

Telecommute ASIC RTL Design Engineers often face challenges like coordinating effectively with remote teams, ensuring version control integrity, and maintaining clear communication on project specifications. These challenges can be mitigated by utilizing robust collaboration tools, adhering to standardized documentation practices, and scheduling regular virtual meetings for design reviews. Additionally, staying proactive in seeking feedback and clarifying requirements helps ensure alignment and prevents costly design iterations.

What is the difference between Telecommute Asic Rtl Design Engineer vs Telecommute Digital IC Design Engineer?

AspectTelecommute Asic Rtl Design EngineerTelecommute Digital IC Design Engineer
CredentialsBachelor's or Master's in Electrical Engineering or Computer Engineering; experience with RTL codingBachelor's or Master's in Electrical Engineering or Computer Engineering; experience with digital circuit design
Work EnvironmentRemote, primarily designing RTL code for ASICsRemote, focusing on digital IC architecture and design
Industry UsageCommon in semiconductor and electronics companies

Both roles often require similar educational backgrounds and work remotely in the semiconductor industry. The main difference lies in their focus: RTL Design Engineers concentrate on writing RTL code for ASICs, while Digital IC Design Engineers work on broader digital circuit architecture. Candidates should choose based on their specific skills and career interests in digital design or RTL coding.

What cities near Clovis, CA are hiring for Telecommute Asic Rtl Design Engineer jobs?

Cities near Clovis, CA with the most Telecommute Asic Rtl Design Engineer job openings:

Telecommute Asic Rtl Design Engineer jobs near you
Infographic showing various Telecommute Asic Rtl Design Engineer job openings in Clovis, CA as of June 2026, with employment types broken down into 17% Full Time, 58% Part Time, 13% Temporary, 8% Contract, and 4% Nights. Highlights an 91% Physical, 7% Hybrid, and 2% Remote job distribution, with an average salary of $149,214 per year, or $71.7 per hour.

[Remote in US] AI Kernel Engineer - RISC-V Software Stack

Fresno, CA • On-site

Mentium Technologies Inc.
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Medical, Dental, Vision, Retirement, PTO

This job post has expired today. Applications are no longer accepted.

Job description

Overview

Mentium Technologies Inc. is seeking an Embedded Software Engineer to develop and optimize high-performance compute software for our custom RISC-V-based vision AI accelerator.

You will work at the intersection of embedded systems, computer architecture, and machine learning, developing high-performance compute kernels, runtime components, libraries, and developer-facing SDK tools. A key part of the role will be efficiently mapping compute-intensive workloads such as convolution, matrix multiplication, and signal-processing operations onto a multicore RISC-V SoC.

The role focuses heavily on vector/SIMD execution, memory optimization, data movement, multicore parallelism, and low-level performance optimization.

Prior RISC-V experience is valuable but not required. Engineers with backgrounds in ARM NEON/SVE, x86 SIMD/AVX, DSP software, GPU kernel programming, embedded performance optimization, or other low-level parallel architectures are encouraged to apply.

You will collaborate closely with RTL design, system architecture, software, and machine learning teams to turn architectural capabilities into a practical, high-performance, and extensible software platform.


Key Responsibilities

  • Develop and optimize high-performance ML and DSP compute kernels, including operations such as convolution, matrix multiplication, activation functions, pooling, image-processing primitives, and related numerical workloads
  • Optimize computationally intensive C/C++ code for vector/SIMD execution, multicore processing, and the SoC memory hierarchy
  • Build reusable compute libraries, runtime components, APIs, and developer-facing components for the Mentium SDK
  • Develop efficient data-movement, memory-management, and workload-scheduling strategies
  • Optimize the use of caches, scratchpad memories, DMA engines, and on-chip memory resources
  • Profile workloads and identify compute, memory-bandwidth, synchronization, and system-level performance bottlenecks
  • Perform low-level performance analysis using profiling, benchmarking, cycle measurements, and hardware/software debugging tools
  • Integrate optimized compute kernels and runtime components into AI model deployment and inference workflows
  • Develop functional tests, performance benchmarks, reference examples, and SDK documentation
  • Collaborate closely with RTL and system-architecture engineers to validate hardware features and improve end-to-end system performance
  • Contribute to the architecture and programming model of Mentium's RISC-V accelerator software stack
  • Evaluate and adapt relevant open-source libraries, runtimes, compiler technologies, and numerical software
  • Help define software requirements and provide feedback that influences future hardware architecture


Required Qualifications

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent practical experience
  • 3+ years of combined relevant industry, graduate research, doctoral research, or applied research experience
  • Strong programming skills in C and/or C++
  • Experience developing or optimizing performance-critical software
  • Experience with at least one area of low-level performance programming, such as:
  • SIMD or vector programming
  • DSP programming
  • GPU kernel programming
  • Assembly or intrinsic-based optimization
  • Performance-critical embedded software
  • Numerical or high-performance computing
  • Solid understanding of computer architecture, memory systems, and parallel processing
  • Experience with performance profiling, benchmarking, low-level debugging, or cycle-level optimization
  • Familiarity with computational workloads such as convolution, matrix multiplication, image processing, signal processing, or other numerical kernels
  • Ability to reason about memory access patterns, data locality, computational efficiency, and hardware utilization
  • Ability to read hardware specifications and work effectively with hardware and RTL engineers
  • Proficiency with Python for testing, automation, benchmarking, tooling, or application development
  • Experience with Git and standard collaborative software-development practices
  • Strong written and verbal communication skills


Preferred Qualifications

Experience in several of the following areas is valuable, but we do not expect candidates to have experience with all of them:

  • RISC-V instruction-set architecture or the RISC-V Vector Extension (RVV)
  • ARM NEON or SVE, x86 SSE/AVX, DSP vector architectures, GPUs, or other SIMD/vector processors
  • Vector intrinsics, assembly programming, compiler intrinsics, or low-level code optimization
  • DSP, image-processing, numerical-computing, or machine-learning kernel development
  • Quantized inference, fixed-point arithmetic, INT8/INT16 computation, FP16/BF16, or other reduced-precision numerical formats
  • DMA, scratchpad memory, cache hierarchies, memory bandwidth optimization, and multicore synchronization
  • Embedded, bare-metal, real-time, or resource-constrained software development
  • Multicore SoCs or heterogeneous compute architectures
  • Open-source RISC-V platforms such as PULP or similar multicore/accelerator systems
  • Machine-learning frameworks and model formats such as PyTorch, TensorFlow, TFLite, or ONNX
  • Compiler and deployment technologies such as LLVM, MLIR, TVM, Deeploy, or related systems
  • SDKs, runtime libraries, numerical libraries, developer tools, or reusable software APIs
  • Hardware-software co-design, SoC development, FPGA prototyping, architectural simulation, or custom accelerator development
  • Open-source software or research software development


Why Join Mentium?

At Mentium, you will work at the intersection of custom silicon, RISC-V, high-performance embedded software, and AI.

You will work directly with the engineers designing the underlying hardware and play a central role in determining how developers and machine-learning workloads interact with our accelerator.

Rather than simply programming an existing processor, you will have the opportunity to influence the hardware-software boundary: identifying architectural bottlenecks, developing optimized compute kernels, evaluating new programming approaches, and providing feedback that can shape future generations of the hardware.

Benefits:

  • Competitive compensation packages
  • Opportunity to work on diverse, cutting-edge AI projects across a range of industries.
  • 401(k)
  • Flexible PTO
  • Full PPO medical, dental, and vision insurance coverage


Apply