RTL Engineer - Networking ASIC Saratoga, CA Full-Time Join an innovative hardware company building ... Design packet buffering, queuing, and scheduling microarchitecture * Implement high-speed ...
RTL Engineer - Networking ASIC Saratoga, CA Full-Time Join an innovative hardware company building ... Design packet buffering, queuing, and scheduling microarchitecture * Implement high-speed ...
ASIC/RTL Design Engineer 5
San Jose, CA ยท On-site
$82 - $86/hr
Hands-on experience with industry ASIC design flow including RTL coding, debugging/verification ... We deliver agile, scalable talent solutions across IT, engineering, life sciences, clinical, and ...
Quick apply
ASIC/RTL Design Engineer 5
San Jose, CA ยท On-site
$82 - $86/hr
Hands-on experience with industry ASIC design flow including RTL coding, debugging/verification ... We deliver agile, scalable talent solutions across IT, engineering, life sciences, clinical, and ...
About the role SambaNova Systems is looking for a Principal RTL Design Engineer to own the ... MS or PhD in EE, CE, or CS with 10+ years of experience in ASIC RTL design
About the role SambaNova Systems is looking for a Principal RTL Design Engineer to own the ... MS or PhD in EE, CE, or CS with 10+ years of experience in ASIC RTL design
ASIC/RTL Design Engineer 2
San Jose, CA ยท On-site
$60 - $62/hr
Hands-on experience in industry ASIC design flow including RTL coding, debugging/verification, and supporting synthesis and timing closure. * Working knowledge of Client cores and other I/O standard ...
Quick apply
ASIC/RTL Design Engineer 2
San Jose, CA ยท On-site
$60 - $62/hr
Hands-on experience in industry ASIC design flow including RTL coding, debugging/verification, and supporting synthesis and timing closure. * Working knowledge of Client cores and other I/O standard ...
ASIC/RTL Design Engineer Primary Skills : RTL coding, TCL coding, Python coding, understanding of different CAD tools (synthesis, lint, CDC, RDC, PrimeTime). Location: San Jose CA Duration : 12 ...
ASIC/RTL Design Engineer Primary Skills : RTL coding, TCL coding, Python coding, understanding of different CAD tools (synthesis, lint, CDC, RDC, PrimeTime). Location: San Jose CA Duration : 12 ...
ASIC RTL/SoC Design Engineer
Fremont, CA ยท On-site
Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...
ASIC RTL/SoC Design Engineer
Fremont, CA ยท On-site
Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...
As a Senior ASIC Design Engineer, you will own the complete RTL design lifecycle from micro-architecture specification through production silicon, working on complex IP design. THE PERSON: The ideal ...
As a Senior ASIC Design Engineer, you will own the complete RTL design lifecycle from micro-architecture specification through production silicon, working on complex IP design. THE PERSON: The ideal ...
ASIC RTL/SoC Design Engineer
Fremont, CA ยท On-site
Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...
ASIC RTL/SoC Design Engineer
Fremont, CA ยท On-site
Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...
Integration RTL Design Engineer
San Jose, CA ยท On-site
$145K/yr
As a Senior ASIC Design Engineer, you will own the complete RTL design lifecycle from micro-architecture specification through production silicon, working on complex IP design. THE PERSON: The ideal ...
Integration RTL Design Engineer
San Jose, CA ยท On-site
$145K/yr
As a Senior ASIC Design Engineer, you will own the complete RTL design lifecycle from micro-architecture specification through production silicon, working on complex IP design. THE PERSON: The ideal ...
ASIC RTL/SoC Design Engineer
San Jose, CA ยท On-site
$110K - $300K/yr
Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...
ASIC RTL/SoC Design Engineer
San Jose, CA ยท On-site
$110K - $300K/yr
Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...
RTL Design Engineer Building AI chips that are hard-coded for individual model architectures. RTL ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
Quick apply
RTL Design Engineer Building AI chips that are hard-coded for individual model architectures. RTL ... both our existing and upcoming ASIC designs. In this role, you will work closely with ...
ASIC RTL/SoC Design Engineer
San Jose, CA ยท On-site
$110K - $300K/yr
Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...
ASIC RTL/SoC Design Engineer
San Jose, CA ยท On-site
$110K - $300K/yr
Lead RTL design, simulation, and verification efforts for TetraMem ASIC/SoC products, ensuring ... Play a mentorship role by guiding and coaching junior engineers, sharing expertise and best ...
Principal RTL Design Engineer
San Jose, CA ยท On-site
Set the technical bar in design reviews and mentor design engineers Required qualifications * BS or MS in EE, CE, or CS with 7+ years (or equivalent) of industry experience in ASIC RTL design
Principal RTL Design Engineer
San Jose, CA ยท On-site
Set the technical bar in design reviews and mentor design engineers Required qualifications * BS or MS in EE, CE, or CS with 7+ years (or equivalent) of industry experience in ASIC RTL design
Staff RTL Engineer - Ethernet Saratoga, CA Full-Time Join a cutting-edge hardware company building ... MSEE with 8-15 years of ASIC/RTL design experience * Strong expertise in Ethernet 802.3 protocols ...
Staff RTL Engineer - Ethernet Saratoga, CA Full-Time Join a cutting-edge hardware company building ... MSEE with 8-15 years of ASIC/RTL design experience * Strong expertise in Ethernet 802.3 protocols ...
Principal RTL Design Engineer
San Jose, CA ยท On-site
$180 - $255/hr
Set the technical bar in design reviews and mentor design engineers Required qualifications * BS or MS in EE, CE, or CS with 7+ years (or equivalent) of industry experience in ASIC RTL design.
Principal RTL Design Engineer
San Jose, CA ยท On-site
$180 - $255/hr
Set the technical bar in design reviews and mentor design engineers Required qualifications * BS or MS in EE, CE, or CS with 7+ years (or equivalent) of industry experience in ASIC RTL design.
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
... RTL designs - Working with design verification and formal verification teams to verify ... front-end ASIC RTL design Tight-knit collaboration skills with excellent written and verbal ...
Description As an ASIC Design Engineer on the Silicon Security team, you will be responsible for the micro-architecture, RTL design and integration of secure subsystems. Your responsibilities will ...
Description As an ASIC Design Engineer on the Silicon Security team, you will be responsible for the micro-architecture, RTL design and integration of secure subsystems. Your responsibilities will ...
RTL Design Engineer, TPU and ML
Sunnyvale, CA ยท On-site
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. * 4 years of experience in ASIC RTL design, with a focus on ...
RTL Design Engineer, TPU and ML
Sunnyvale, CA ยท On-site
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. * 4 years of experience in ASIC RTL design, with a focus on ...
Telecommute Asic Rtl Design Engineer information
See Santa Clara, CA salary details
$110.4K - $121.9K
16% of jobs
$121.9K - $133.5K
3% of jobs
$133.5K - $145K
4% of jobs
$148.4K is the 25th percentile. Wages below this are outliers.
$145K - $156.5K
6% of jobs
The median wage is $163.8K / yr.
$156.5K - $168.1K
33% of jobs
$168.1K - $179.6K
3% of jobs
$179.6K - $191.1K
2% of jobs
$198.7K is the 75th percentile. Wages above this are outliers.
$191.1K - $202.6K
12% of jobs
$202.6K - $214.2K
5% of jobs
$214.2K - $225.7K
4% of jobs
$225.7K - $237.2K
12% of jobs
$110.4K
$176.4K
$237.2K
How much do telecommute asic rtl design engineer jobs pay per year?
What is a telecommute ASIC RTL design engineer?
What are the key skills and qualifications needed to thrive as a telecommute ASIC RTL design engineer?
What are some common challenges faced by telecommute ASIC RTL design engineers, and how can they be addressed?
What is the difference between Telecommute Asic Rtl Design Engineer vs Telecommute Digital IC Design Engineer?
| Aspect | Telecommute Asic Rtl Design Engineer | Telecommute Digital IC Design Engineer |
|---|---|---|
| Credentials | Bachelor's or Master's in Electrical Engineering or Computer Engineering; experience with RTL coding | Bachelor's or Master's in Electrical Engineering or Computer Engineering; experience with digital circuit design |
| Work Environment | Remote, primarily designing RTL code for ASICs | Remote, focusing on digital IC architecture and design |
| Industry Usage | Common in semiconductor and electronics companies |
Both roles often require similar educational backgrounds and work remotely in the semiconductor industry. The main difference lies in their focus: RTL Design Engineers concentrate on writing RTL code for ASICs, while Digital IC Design Engineers work on broader digital circuit architecture. Candidates should choose based on their specific skills and career interests in digital design or RTL coding.
What are the most commonly searched types of Asic Rtl Design Engineer jobs in Santa Clara, CA?
The most popular types of Asic Rtl Design Engineer jobs in Santa Clara, CA are:
What cities near Santa Clara, CA are hiring for Telecommute Asic Rtl Design Engineer jobs?
Cities near Santa Clara, CA with the most Telecommute Asic Rtl Design Engineer job openings:
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Re-posted yesterday
Job description
Saratoga, CA
Full-Time
Join an innovative hardware company building next-generation Networking ASICs that power large-scale AI training and inference.
We are seeking experienced RTL Engineers to architect and implement high-performance networking chips focused on low latency, QoS, and scalability.
Responsibilities-
Design packet buffering, queuing, and scheduling microarchitecture
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Implement high-speed networking ASIC RTL (SystemVerilog/Verilog)
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Optimize pipelined architectures for performance and latency
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Support Ethernet, IP protocols, and high-speed interconnects (e.g., UCIe)
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Collaborate with verification teams for testing and validation
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BE/ME with 8โ15 years of ASIC RTL design experience
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Strong expertise in SystemVerilog & Verilog
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Experience with scheduling, arbitration & QoS mechanisms
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Solid understanding of ASIC design flow (simulation, synthesis, timing)
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Background in Ethernet and IP networking protocols
If youโre passionate about building high-speed networking silicon for AI infrastructure, apply today.