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Remote Asic Rtl Design Engineer Jobs in Santa Clara, CA

Purple Hires Inc

Lead ASIC DFT Engineer

San Jose, CA · Remote

Title - Lead ASIC DFT Engineer Location - Remote (must be aligned with PST time zone) Below is the ... Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to ...

Meta

ASIC Engineer, Power

Sunnyvale, CA · On-site +1

$146K/yr

As an ASIC Engineer specializing in power on the EDA Infrastructure team, you will develop and ... Collaborate with RTL design, physical design, and verification teams to identify and resolve power ...

Cornelis Networks

PCIe ASIC Design Engineer

San Jose, CA · On-site +1

... remote roles. Cornelis Networks is hiringa Senior ASIC Design Engineer to lead the design and ... Debug functional and performance issues at RTL, gate-level, and silicon. * Ensure compliance with ...

MatX

ASIC/SOC CAD Engineer

Mountain View, CA · On-site +1

$175K - $362K/yr

Develop, maintain, and continuously improve MatX's Physical Design flow, from RTL to GDSII flow ... Remote Perks We work remotely Monday & Friday, supported by home-tech setup, and remote wifi ...

Meta

ASIC Engineer, Design Verification

Sunnyvale, CA · On-site +1

$114K/yr

ASIC Engineer, Design Verification Responsibilities: * Define and implement block, IP, and SoC ... Debug and root-cause functional failures in RTL designs, partnering closely with the ASIC design ...

Tensordyne

Principal ASIC Architect

Sunnyvale, CA · On-site +1

Work closely with external engineering partners, ASIC design engineers, ASIC design verification ... Strong Verilog programming skills, and experience with RTL verification, and performance modeling.

AttoTude

MMIC Design Engineer

Menlo Park, CA · On-site +1

$160K - $250K/yr

We are seeking a highly experienced THz IC Design Engineer to join our growing team. In this role ... Understanding tradeoff at the device level for high performance ASIC implementation * Ability to ...

AttoTude

MMIC Design Engineer

Menlo Park, CA · On-site +1

We are seeking a highly experienced THz IC Design Engineer to join our growing team. In this role ... Understanding tradeoff at the device level for high performance ASIC implementation * Ability to ...

Meta

ASIC Engineer, Design Verification

Sunnyvale, CA · On-site +1

$146K/yr

Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for ...

MatX

SOC Integration Engineer

Mountain View, CA · Remote

$175K - $450K/yr

... SOC RTL design. * Partner with SubSystem owners within the Design team to facilitate block ... Remote Perks We work remotely Monday & Friday, supported by home-tech setup, and remote wifi ...

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All JobsAsic Rtl Design Engineer JobsRemote Asic Rtl Design Engineer JobsRemote Asic Rtl Design Engineer Jobs in Santa Clara, CA

Remote Asic Rtl Design Engineer information

See Santa Clara, CA salary details

$110.4K

$176.4K

$237.2K

How much do remote asic rtl design engineer jobs pay per year?

As of Aug 20, 2026, the average yearly pay for remote asic rtl design engineer in Santa Clara, CA is $176,395.00, according to ZipRecruiter salary data. Most workers in this role earn between $154,400.00 and $211,400.00 per year, depending on experience, location, and employer.

What is a remote ASIC RTL design engineer?

A Remote ASIC RTL Design Engineer is a professional who specializes in designing the Register Transfer Level (RTL) code for Application-Specific Integrated Circuits (ASICs) while working remotely. Their main responsibilities include creating and verifying digital circuit designs using hardware description languages such as Verilog or VHDL. These engineers collaborate with hardware teams to ensure functionality, performance, and power requirements are met, all while operating from a location outside of a traditional office setting. They often use remote collaboration tools and simulation software to review and validate designs before fabrication.

What are the key skills and qualifications needed to thrive as a remote ASIC RTL design engineer?

To thrive as a Remote ASIC RTL Design Engineer, you need a solid background in digital design, computer engineering, and hardware description languages like Verilog or VHDL, often supported by a relevant degree. Proficiency with industry-standard EDA tools such as Synopsys, Cadence, or Mentor Graphics, as well as experience with simulation, synthesis, and version control systems, is crucial. Strong problem-solving, self-motivation, and effective remote communication skills distinguish top performers in this role. These skills ensure accurate, efficient design cycles and effective collaboration across distributed teams, leading to successful chip delivery.

What are some common challenges faced by remote ASIC RTL design engineers, and how can they be addressed?

Remote ASIC RTL Design Engineers often face challenges such as coordinating with distributed teams across different time zones and ensuring effective communication during complex design phases. To address these issues, it’s important to establish clear documentation practices, utilize collaboration tools like version control and video conferencing, and schedule regular check-ins with team members. Additionally, staying proactive in seeking feedback and clarifying design specifications helps ensure alignment and reduces misunderstandings. Building strong virtual relationships with verification and backend teams can also streamline the handoff process and overall project flow.

What is the difference between Remote Asic Rtl Design Engineer vs Remote Digital IC Design Engineer?

AspectRemote Asic Rtl Design EngineerRemote Digital IC Design Engineer
Primary FocusRegister Transfer Level (RTL) design for ASICsDigital integrated circuit design at the IC level
Skills & CertificationsHDL (Verilog/VHDL), EDA tools, verificationHDL, circuit simulation, verification, FPGA experience
Work EnvironmentASIC design teams, hardware developmentIC design teams, semiconductor industry
Industry UsageUsed in ASIC development for various applicationsUsed in digital IC manufacturing and prototyping

Both roles involve digital design and HDL skills, but the Remote Asic Rtl Design Engineer focuses on RTL coding for ASICs, while the Remote Digital IC Design Engineer covers broader digital IC design, including FPGA and chip-level work. They share similar credentials and work environments, often overlapping in semiconductor companies.

What are the most commonly searched types of Asic Rtl Design Engineer jobs in Santa Clara, CA?

The most popular types of Asic Rtl Design Engineer jobs in Santa Clara, CA are:

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Remote Asic Rtl Design Engineer jobs near you

RTL Design Engineer - Wireless SoC

Vkore Solutions

San Jose, CA • Remote

$55 - $60/hr

Contractor

Re-posted 18 days ago

Job description

Job Title: RTL Design Engineer – Wireless SoC

Location: Remote

Job Type: Contract

 

Job Description

We are seeking an experienced RTL Design Engineer to work on next-generation wireless SoC development. The ideal candidate will design and implement high-performance digital blocks and work closely with architecture, analog/mixed-signal, and verification teams to deliver production-quality silicon.

Key Responsibilities

  • Design, implement, and verify digital blocks for wireless SoCs using SystemVerilog/Verilog
  • Translate architectural and algorithmic specifications into synthesizable RTL
  • Implement DSP blocks such as filtering, FFT/IFFT, beamforming, etc.
  • Develop RTL for SoC components including interfaces, clock/reset, power management, and debug logic
  • Work with internal and external IP integration into chip-level designs
  • Collaborate with AMS teams on digital-analog interfaces, calibration logic, and control systems
  • Drive PPA (power, performance, area) optimization and support timing closure with backend teams
  • Participate in design reviews, integration, synthesis, and timing closure activities
  • Support silicon bring-up and lab validation of digital subsystems

Required Skills

  • 5+ years of hands-on RTL design experience (SystemVerilog / Verilog)
  • Strong understanding of micro-architecture and RTL implementation from specs
  • Experience in DSP hardware implementation (filtering, FFT, etc.)
  • Knowledge of SoC design flows: CDC, power domains, timing constraints, formal verification
  • Experience with synthesis, linting, simulation, and STA tools
  • Understanding of DFT concepts (scan, BIST)
  • Strong debugging and problem-solving skills
  • Good communication and ability to work in cross-functional teams

Preferred Skills

  • Experience in wireless SoC domains (Wi-Fi, cellular, mmWave, satellite, etc.)
  • RTL design of datapath, FIFO, DMA, arbitration, and SoC bus (AXI/AHB)
  • DSP modeling experience (MATLAB / Python / C++) and RTL conversion
  • Post-silicon debug and chip bring-up experience
  • Exposure to analog-mixed signal interfaces and calibration logic
  • Experience in distributed/global team environments