S. in Electrical Engineering, Computer Engineering, or Computer Science * 5+ years of experience in ASIC RTL design * Solid foundation in computer architecture and digital logic design * Strong ...
S. in Electrical Engineering, Computer Engineering, or Computer Science * 5+ years of experience in ASIC RTL design * Solid foundation in computer architecture and digital logic design * Strong ...
We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed ... Own ASIC RTL delivery schedules across major milestones by tracking, monitoring, and reporting ...
Quick apply
We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed ... Own ASIC RTL delivery schedules across major milestones by tracking, monitoring, and reporting ...
We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed ... Own ASIC RTL delivery schedules across major milestones by tracking, monitoring, and reporting ...
We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed ... Own ASIC RTL delivery schedules across major milestones by tracking, monitoring, and reporting ...
Principal RTL Design Engineer
Austin, TX · On-site
B.S. in Electrical Engineering, Computer Engineering, or Computer Science * 7+ years of industry experience in ASIC RTL design * Mastery of synthesizable SystemVerilog for high-speed, high ...
Principal RTL Design Engineer
Austin, TX · On-site
B.S. in Electrical Engineering, Computer Engineering, or Computer Science * 7+ years of industry experience in ASIC RTL design * Mastery of synthesizable SystemVerilog for high-speed, high ...
Senior RTL Design Engineer
Austin, TX · On-site
$120 - $200/hr
S. in Electrical Engineering, Computer Engineering, or Computer Science * 5+ years of experience in ASIC RTL design * Solid foundation in computer architecture and digital logic design * Strong ...
Senior RTL Design Engineer
Austin, TX · On-site
$120 - $200/hr
S. in Electrical Engineering, Computer Engineering, or Computer Science * 5+ years of experience in ASIC RTL design * Solid foundation in computer architecture and digital logic design * Strong ...
Senior RTL Design Engineer
Austin, TX · On-site
$120K - $200K/yr
S. in Electrical Engineering, Computer Engineering, or Computer Science * 5+ years of experience in ASIC RTL design * Solid foundation in computer architecture and digital logic design * Strong ...
Senior RTL Design Engineer
Austin, TX · On-site
$120K - $200K/yr
S. in Electrical Engineering, Computer Engineering, or Computer Science * 5+ years of experience in ASIC RTL design * Solid foundation in computer architecture and digital logic design * Strong ...
Principal RTL Design Engineer
Austin, TX · On-site
$180K - $255K/yr
B.S. in Electrical Engineering, Computer Engineering, or Computer Science * 7+ years of industry experience in ASIC RTL design * Mastery of synthesizable SystemVerilog for high-speed, high ...
Principal RTL Design Engineer
Austin, TX · On-site
$180K - $255K/yr
B.S. in Electrical Engineering, Computer Engineering, or Computer Science * 7+ years of industry experience in ASIC RTL design * Mastery of synthesizable SystemVerilog for high-speed, high ...
Principal RTL Design Engineer
Austin, TX · On-site
$180 - $255/hr
S. in Electrical Engineering, Computer Engineering, or Computer Science * 7+ years of industry experience in ASIC RTL design * Mastery of synthesizable SystemVerilog for high‑speed ...
Principal RTL Design Engineer
Austin, TX · On-site
$180 - $255/hr
S. in Electrical Engineering, Computer Engineering, or Computer Science * 7+ years of industry experience in ASIC RTL design * Mastery of synthesizable SystemVerilog for high‑speed ...
Senior Manager, ASIC Design Engineering
Austin, TX · On-site +1
Cornelis Networks islooking for aSenior ASIC Design Engineering Managerto lead and grow our RTL design engineering team.Reporting to the VP of ASIC Engineering,with direct exposure toexecutive ...
Senior Manager, ASIC Design Engineering
Austin, TX · On-site +1
Cornelis Networks islooking for aSenior ASIC Design Engineering Managerto lead and grow our RTL design engineering team.Reporting to the VP of ASIC Engineering,with direct exposure toexecutive ...
ASIC Digital Design, Architect - 18388
Austin, TX · On-site
$181K/yr
Defining and developing ASIC RTL design and verification at both chip and block levels. * Creating ... Mentoring engineers and promoting best practices, technical excellence, and continuous improvement.
ASIC Digital Design, Architect - 18388
Austin, TX · On-site
$181K/yr
Defining and developing ASIC RTL design and verification at both chip and block levels. * Creating ... Mentoring engineers and promoting best practices, technical excellence, and continuous improvement.
RTL Design Engineer
Austin, TX · On-site
$120K - $225K/yr
We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.
RTL Design Engineer
Austin, TX · On-site
$120K - $225K/yr
We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.
RTL Design Engineer
$120K - $225K/yr
We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.
Quick apply
RTL Design Engineer
$120K - $225K/yr
We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.
RTL Design Engineer
$120K - $225K/yr
We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.
RTL Design Engineer
$120K - $225K/yr
We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.
ASIC Design Engineer - Hardware
Austin, TX · On-site
$116 - $180/hr
## ASIC Design Engineer - HardwareApplylocations: US, TX, Austintime type: Full timeposted on: Posted ... Run and debug RTL checks to ensure design quality (e.g., cross clock domains (CDC), clocks, reset ...
ASIC Design Engineer - Hardware
Austin, TX · On-site
$116 - $180/hr
## ASIC Design Engineer - HardwareApplylocations: US, TX, Austintime type: Full timeposted on: Posted ... Run and debug RTL checks to ensure design quality (e.g., cross clock domains (CDC), clocks, reset ...
SR. RTL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building ... ASIC/SoC system integration experience * Experience with embedded CPU subsystems * Experience with ...
SR. RTL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building ... ASIC/SoC system integration experience * Experience with embedded CPU subsystems * Experience with ...
RTL Design Engineer
Austin, TX · On-site
$134K/yr
If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. This is an exciting position in the world class ...
RTL Design Engineer
Austin, TX · On-site
$134K/yr
If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. This is an exciting position in the world class ...
Own full lifecycle recruiting for hardware roles across Design Verification, ASIC/RTL design, physical design, and PCB/systems engineering * Keep feedback loops tight across interviewers and ...
Own full lifecycle recruiting for hardware roles across Design Verification, ASIC/RTL design, physical design, and PCB/systems engineering * Keep feedback loops tight across interviewers and ...
Senior Engineer, GPU RTL Design
Austin, TX · On-site
Role and Responsibilities As an Engineer or Senior or Staff GPU RTL Design Engineer, you will ... Experience with front-end ASIC design flows, including linting, synthesis, timing analysis, and ...
Senior Engineer, GPU RTL Design
Austin, TX · On-site
Role and Responsibilities As an Engineer or Senior or Staff GPU RTL Design Engineer, you will ... Experience with front-end ASIC design flows, including linting, synthesis, timing analysis, and ...
RTL Design Engineer
$134K/yr
If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. This is an exciting position in the world class ...
RTL Design Engineer
$134K/yr
If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. This is an exciting position in the world class ...
ASIC Digital Design, Sr Staff Engineer - 18384
Austin, TX · On-site
$138K/yr
You bring strong RTL design and verification expertise to solve challenging ASIC design problems. * You enjoy collaborating across engineering teams to improve performance, power, quality, and ...
ASIC Digital Design, Sr Staff Engineer - 18384
Austin, TX · On-site
$138K/yr
You bring strong RTL design and verification expertise to solve challenging ASIC design problems. * You enjoy collaborating across engineering teams to improve performance, power, quality, and ...
Telecommute Asic Rtl Design Engineer information
See Leander, TX salary details
$89.8K - $99.2K
16% of jobs
$99.2K - $108.6K
3% of jobs
$108.6K - $118K
4% of jobs
$120.7K is the 25th percentile. Wages below this are outliers.
$118K - $127.3K
6% of jobs
The median wage is $133.2K / yr.
$127.3K - $136.7K
33% of jobs
$136.7K - $146.1K
3% of jobs
$146.1K - $155.5K
2% of jobs
$161.7K is the 75th percentile. Wages above this are outliers.
$155.5K - $164.9K
12% of jobs
$164.9K - $174.3K
5% of jobs
$174.3K - $183.6K
4% of jobs
$183.6K - $193K
12% of jobs
$89.8K
$143.5K
$193K
How much do telecommute asic rtl design engineer jobs pay per year?
What are the most commonly searched types of Asic Rtl Design Engineer jobs in Leander, TX?
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Cities near Leander, TX with the most Telecommute Asic Rtl Design Engineer job openings:
Job description
The RTL design team builds the compute datapath, on-chip network, and memory subsystems inside SambaNova's RDU AI accelerator. Their work spans microarchitecture through tape-out: RTL implementation, PPA trade-offs, quality gates like lint, CDC, and LEC, and timing closure withÂ
About the roleSambaNova RTL Design Engineers design component units of the Reconfigurable Dataflow Unit (RDU) ASICs behind our AI acceleration systems. You'll own blocks within a larger subsystem, contributing sections of the microarchitecture specification, writing and debugging the RTL, and carrying your blocks through implementation, tape-out, and silicon bring-up. You'll work alongside principal engineers, architects, design verification, and physical design, and take on larger blocks as you build depth in our architecture
Required Qualifications- B.S. in Electrical Engineering, Computer Engineering, or Computer Science
- 5+ years of experience in ASIC RTL design
- Solid foundation in computer architecture and digital logic design
- Strong SystemVerilog RTL design skills for high-speed, high-performance ASICs
- Experience making design decisions that trade off power, performance, and area
- Knowledge of industry-standard interconnects and protocols including AXI, PCIe, Ethernet, and HBM or DDR
- Experience with digital logic synthesis tools and static timing analysis
- Proficiency with industry-standard tools for linting, clock domain crossing, and logical equivalence checking
- Experience implementing SystemVerilog Assertions to check design intent
- Familiarity with tools and simulators for hardware performance analysis and tuning
- Familiarity with Git for managing release cycles
- Scripting skills in Python and Linux shell
- M.S. or Ph.D. in Electrical Engineering, Computer Engineering, or Computer Science
- Exposure to a full ASIC development cycle through tape-out and production silicon
- Interest in or knowledge of AI workload acceleration techniques
- Experience with low-power design techniques such as clock gating and DVFS at advanced process nodes
- Exposure to emulation or FPGA prototyping platforms for pre-silicon validation