We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed ... Own ASIC RTL delivery schedules across major milestones by tracking, monitoring, and reporting ...
Quick apply
We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed ... Own ASIC RTL delivery schedules across major milestones by tracking, monitoring, and reporting ...
Quick apply
We're seeking engineers who are energized by working on cutting-edge ASIC design and distributed ... Own ASIC RTL delivery schedules across major milestones by tracking, monitoring, and reporting ...
Austin, TX · On-site +1
Cornelis Networks islooking for aSenior ASIC Design Engineering Managerto lead and grow our RTL design engineering team.Reporting to the VP of ASIC Engineering,with direct exposure toexecutive ...
Austin, TX · On-site +1
Cornelis Networks islooking for aSenior ASIC Design Engineering Managerto lead and grow our RTL design engineering team.Reporting to the VP of ASIC Engineering,with direct exposure toexecutive ...
Cornelis Networks islooking for aSenior ASIC Design Engineering Managerto lead and grow our RTL design engineering team.Reporting to the VP of ASIC Engineering,with direct exposure toexecutive ...
Quick apply
Cornelis Networks islooking for aSenior ASIC Design Engineering Managerto lead and grow our RTL design engineering team.Reporting to the VP of ASIC Engineering,with direct exposure toexecutive ...
Austin, TX · On-site
$120K - $225K/yr
We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.
Quick apply
Austin, TX · On-site
$120K - $225K/yr
We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.
$120K - $225K/yr
We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.
$120K - $225K/yr
We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.
$120K - $225K/yr
We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.
$120K - $225K/yr
We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.
Austin, TX · On-site
$116 - $189.75/hr
Run RTL checks to ensure design quality, including cross clock domains, clocks, reset, latency, etc. * Design and implement RTL features, working closely with experienced engineers. * Collaborate ...
Austin, TX · On-site
$116 - $189.75/hr
Run RTL checks to ensure design quality, including cross clock domains, clocks, reset, latency, etc. * Design and implement RTL features, working closely with experienced engineers. * Collaborate ...
SR. RTL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building ... ASIC/SoC system integration experience * Experience with embedded CPU subsystems * Experience with ...
SR. RTL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building ... ASIC/SoC system integration experience * Experience with embedded CPU subsystems * Experience with ...
Role and Responsibilities As an Engineer or Senior or Staff GPU RTL Design Engineer, you will ... Experience with front-end ASIC design flows, including linting, synthesis, timing analysis, and ...
Role and Responsibilities As an Engineer or Senior or Staff GPU RTL Design Engineer, you will ... Experience with front-end ASIC design flows, including linting, synthesis, timing analysis, and ...
$134K/yr
If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. This is an exciting position in the world class ...
$134K/yr
If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. This is an exciting position in the world class ...
Austin, TX · On-site
$124 - $208.40/hr
Role and Responsibilities As an Engineer or Senior or Staff GPU RTL Design Engineer, you will ... Experience with front-end ASIC design flows, including linting, synthesis, timing analysis, and ...
Austin, TX · On-site
$124 - $208.40/hr
Role and Responsibilities As an Engineer or Senior or Staff GPU RTL Design Engineer, you will ... Experience with front-end ASIC design flows, including linting, synthesis, timing analysis, and ...
$134K/yr
If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. This is an exciting position in the world class ...
$134K/yr
If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. This is an exciting position in the world class ...
Austin, TX · On-site
If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. This is an exciting position in the world class ...
Austin, TX · On-site
If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. This is an exciting position in the world class ...
$120K - $225K/yr
We're hiring experienced RTL Design Engineers to play a key role in designing and implementing the components that will bring our next-generation AI processors to life. About Us: Mythic is building ...
$120K - $225K/yr
We're hiring experienced RTL Design Engineers to play a key role in designing and implementing the components that will bring our next-generation AI processors to life. About Us: Mythic is building ...
$146K/yr
ASIC Engineer, Design Responsibilities ... Develop micro-architecture, RTL coding, and design verification for complex IPs. * Work with ...
$146K/yr
ASIC Engineer, Design Responsibilities ... Develop micro-architecture, RTL coding, and design verification for complex IPs. * Work with ...
$120K - $225K/yr
We're hiring experienced RTL Design Engineers to play a key role in designing and implementing the components that will bring our next-generation AI processors to life. About Us: Mythic is building ...
Quick apply
$120K - $225K/yr
We're hiring experienced RTL Design Engineers to play a key role in designing and implementing the components that will bring our next-generation AI processors to life. About Us: Mythic is building ...
$120K - $225K/yr
We're hiring experienced RTL Design Engineers to play a key role in designing and implementing the components that will bring our next-generation AI processors to life. About Us: Mythic is building ...
$120K - $225K/yr
We're hiring experienced RTL Design Engineers to play a key role in designing and implementing the components that will bring our next-generation AI processors to life. About Us: Mythic is building ...
Austin, TX · On-site
$156K/yr
As a CPU Core RTL Design Engineer, you will help design and optimize next-generation high ... Experience with Verilog/SystemVerilog RTL development in CPU, SoC, or ASIC environments * Strong ...
Austin, TX · On-site
$156K/yr
As a CPU Core RTL Design Engineer, you will help design and optimize next-generation high ... Experience with Verilog/SystemVerilog RTL development in CPU, SoC, or ASIC environments * Strong ...
Austin, TX · On-site
If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. This is an exciting position in the world class ...
Austin, TX · On-site
If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. This is an exciting position in the world class ...
Asic Design Engineer Location: Mountain View CA (Remote) Note: Seeking candidate with Fusion ... Good in understanding RTL Design and Digital concepts * Strong experience with EDA tools: Fusion ...
Asic Design Engineer Location: Mountain View CA (Remote) Note: Seeking candidate with Fusion ... Good in understanding RTL Design and Digital concepts * Strong experience with EDA tools: Fusion ...
$89.8K - $99.2K
16% of jobs
$99.2K - $108.6K
3% of jobs
$108.6K - $118K
4% of jobs
$120.7K is the 25th percentile. Wages below this are outliers.
$118K - $127.3K
6% of jobs
The median wage is $133.2K / yr.
$127.3K - $136.7K
33% of jobs
$136.7K - $146.1K
3% of jobs
$146.1K - $155.5K
2% of jobs
$161.7K is the 75th percentile. Wages above this are outliers.
$155.5K - $164.9K
12% of jobs
$164.9K - $174.3K
5% of jobs
$174.3K - $183.6K
4% of jobs
$183.6K - $193K
12% of jobs
$89.8K
$143.5K
$193K
| Aspect | Temporary Asic Rtl Design Engineer | Temporary FPGA Design Engineer |
|---|---|---|
| Primary Focus | Designing RTL code for ASIC chips | Designing FPGA logic and configurations |
| Skills & Certifications | Verilog/VHDL, ASIC design flow, simulation tools | Verilog/VHDL, FPGA development tools, synthesis |
| Work Environment | Semiconductor companies, ASIC design teams | FPGA development labs, prototyping environments |
| Industry Usage | Used in high-volume chip manufacturing | Used for prototyping, testing, and low-volume products |
Both roles involve RTL design using Verilog or VHDL, but the Temporary Asic Rtl Design Engineer focuses on ASIC chip development, while the Temporary FPGA Design Engineer specializes in FPGA-based prototyping and testing. The choice depends on whether the project aims for mass production or flexible, rapid development.
Full-time
Medical, Dental, Vision, Life, Retirement, PTO
Posted 4 days ago
At Cornelis we’re building the future of AI and HPC networking with an AI-first approach to silicon and software development. We’re seeking engineers who are energized by working on cutting-edge ASIC design and distributed software systems, and who are motivated to push the boundaries on how AI can transform everything from chip architecture to system performance at scale.
At Cornelis we’re building the future of AI and HPC networking with an AI-first approach to silicon and software development. We’re seeking engineers who are energized by working on cutting-edge ASIC design and distributed software systems, and who are motivated to push the boundaries on how AI can transform everything from chip architecture to system performance at scale.
Cornelis Networks delivers the world’s highest performance scale-out networking solutions for AI and HPC datacenters. Our differentiated architecture seamlessly integrates hardware, software and system level technologies to maximize the efficiency of GPU, CPU and accelerator-based compute clusters at any scale. Our solutions drive breakthroughs in AI & HPC workloads, empowering our customers to push the boundaries of innovation. Backed by top-tier venture capital and strategic investors, we are committed to innovation, performance and scalability - solving the world’s most demanding computational challenges with our next-generation networking solutions.
We are a fast-growing, forward-thinking team of architects, engineers, and business professionals with a proven track record of building successful products and companies. As a global organization, our team spans multiple U.S. states and six countries, and we continue to expand with exceptional talent in onsite, hybrid, and fully remote roles.
Cornelis Networks is looking for a Senior ASIC Design Engineering Manager to lead and grow our RTL design engineering team. Reporting to the VP of ASIC Engineering, with direct exposure to executive leadership, this leader will manage a team of talented design engineers and drive full-lifecycle development of Cornelis’ next-generation, high-performance networking ASICs. The role is accountable for building and driving RTL implementation schedules across all SoC subsystems and full-chip milestones. Success requires deep hands-on expertise in advanced RTL design implementation, methodologies, and SoC flows, from microarchitecture definition through RTL delivery, tape-out readiness, and cross-functional execution with Architecture, Design Verification, Emulation, and Physical Design. This leader will also own headcount planning, hiring, and organizational strategy to build a nimble, efficient, world-class design team. Exposure to AI-based design flows and methodology is preferred.
This role is intended for a senior engineering leader who can combine hands-on ASIC RTL design expertise with disciplined program execution, cross-functional coordination, and team building at scale.
Key Responsibilities
Minimum Qualifications
Preferred Qualifications
Location: This is a remote position for employees residing within the United States.
We offer a competitive compensation package that includes equity, cash, and incentives, along with health and retirement benefits. Our dynamic, flexible work environment provides the opportunity to collaborate with some of the most influential names in the semiconductor industry.
At Cornelis Networks your base salary is only one component of your comprehensive total rewards package. Your base pay will be determined by factors such as your skills, qualifications, experience, and location relative to the hiring range for the position. Depending on your role, you may also be eligible for performance-based incentives, including an annual bonus or sales incentives.
In addition to your base pay, you’ll have access to a broad range of benefits, including medical, dental, and vision coverage, as well as disability and life insurance, a dependent care flexible spending account, accidental injury insurance, and pet insurance. We also offer generous paid holidays, 401(k) with company match, and Open Time Off (OTO) for regular full-time exempt employees. Other paid time off benefits include sick time, bonding leave, and pregnancy disability leave.
Cornelis Networks does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. Cornelis Networks is an equal opportunity employer, and all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity or expression, pregnancy, age, national origin, disability status, genetic information, protected veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
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Software development
51 - 200 Employees
Wayne, PA, US
2019