Design Engineering Architect
Austin, TX · On-site
Guide and mentor a team of RTL design engineers, fostering a collaborative and innovative environment. Design & Microarchitecture: Define and develop microarchitectural features for IPs and ...
Design Engineering Architect
Austin, TX · On-site
Guide and mentor a team of RTL design engineers, fostering a collaborative and innovative environment. Design & Microarchitecture: Define and develop microarchitectural features for IPs and ...
Design Engineering Architect
Austin, TX · On-site
Guide and mentor a team of RTL design engineers, fostering a collaborative and innovative environment. Design & Microarchitecture: Define and develop microarchitectural features for IPs and ...
Design Engineering Architect
Austin, TX · On-site
Guide and mentor a team of RTL design engineers, fostering a collaborative and innovative environment. Design & Microarchitecture: Define and develop microarchitectural features for IPs and ...
TITLE :- System IP/RTL Design Engineer LOCATION Austin, TX (Onsite) DURATION 6+ Months (May get extend) MODE OF INTERVIEW Onsite RATE $90 per hour on W2 Key responsibilities include: * Work on RTL ...
TITLE :- System IP/RTL Design Engineer LOCATION Austin, TX (Onsite) DURATION 6+ Months (May get extend) MODE OF INTERVIEW Onsite RATE $90 per hour on W2 Key responsibilities include: * Work on RTL ...
GPU Design Engineer
Austin, TX · On-site
Provide hands-on technical leadership across RTL design and design verification, including ... Extensive experience delivering complex GPU, CPU, and/or ASIC designs from micro-architecture ...
GPU Design Engineer
Austin, TX · On-site
Provide hands-on technical leadership across RTL design and design verification, including ... Extensive experience delivering complex GPU, CPU, and/or ASIC designs from micro-architecture ...
As an ASIC Engineer specializing in architecture, performance and modeling, you will define and ... Collaborate with architecture, RTL design, and physical design teams to translate performance ...
As an ASIC Engineer specializing in architecture, performance and modeling, you will define and ... Collaborate with architecture, RTL design, and physical design teams to translate performance ...
As an ASIC Engineer specializing in architecture, performance and modeling, you will define and ... Collaborate with architecture, RTL design, and physical design teams to translate performance ...
As an ASIC Engineer specializing in architecture, performance and modeling, you will define and ... Collaborate with architecture, RTL design, and physical design teams to translate performance ...
Senior CPU RTL Design Engineer
Austin, TX · On-site
As a CPU RTL Logic Design Engineer your responsibilities will include but are not limited to: Collaborates, drives and develops logic design, register transfer level (RTL) coding, and simulation for ...
Senior CPU RTL Design Engineer
Austin, TX · On-site
As a CPU RTL Logic Design Engineer your responsibilities will include but are not limited to: Collaborates, drives and develops logic design, register transfer level (RTL) coding, and simulation for ...
SR. ASIC DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... RTL design, chip bring-up, and post-silicon validation experience * Ability to work in a dynamic ...
SR. ASIC DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... RTL design, chip bring-up, and post-silicon validation experience * Ability to work in a dynamic ...
Design Engineer III
Austin, TX · On-site
Job Title: Core Engineering - Design Engineer III Duration: 12 months with possible extension ... Minimum Qualifications Demonstrated experience with RTL-to-GDSII design flow usage and development ...
Design Engineer III
Austin, TX · On-site
Job Title: Core Engineering - Design Engineer III Duration: 12 months with possible extension ... Minimum Qualifications Demonstrated experience with RTL-to-GDSII design flow usage and development ...
As an ASIC Engineer specializing in performance and modeling, you will define and drive the ... Collaborate with architecture, RTL design, and physical design teams to translate performance ...
As an ASIC Engineer specializing in performance and modeling, you will define and drive the ... Collaborate with architecture, RTL design, and physical design teams to translate performance ...
PCIe ASIC Design Engineer
Austin, TX · On-site
Debug functional and performance issues at RTL, gate-level, and silicon. * Ensure compliance with ... Engineering, or related field. * 10+ years of industry experience in ASIC/SoC design with a focus ...
PCIe ASIC Design Engineer
Austin, TX · On-site
Debug functional and performance issues at RTL, gate-level, and silicon. * Ensure compliance with ... Engineering, or related field. * 10+ years of industry experience in ASIC/SoC design with a focus ...
Design Engineer III
Austin, TX · On-site
Job Title: Core Engineering - Design Engineer III Duration: 12 months with possible extension ... Minimum Qualifications Demonstrated experience with RTL-to-GDSII design flow usage and development ...
Design Engineer III
Austin, TX · On-site
Job Title: Core Engineering - Design Engineer III Duration: 12 months with possible extension ... Minimum Qualifications Demonstrated experience with RTL-to-GDSII design flow usage and development ...
Senior CPU RTL Design Engineer
Austin, TX · On-site
As a CPU RTL Logic Design Engineer your responsibilities will include but are not limited to: • Collaborates, drives and develops logic design, register transfer level (RTL) coding, and simulation ...
Senior CPU RTL Design Engineer
Austin, TX · On-site
As a CPU RTL Logic Design Engineer your responsibilities will include but are not limited to: • Collaborates, drives and develops logic design, register transfer level (RTL) coding, and simulation ...
Senior ASIC Physical Design Engineer
Austin, TX · On-site
$165K - $241K/yr
Your Impact As a Physical Design Engineer, you will play a key role in the full RTL-to-GDSII ... Own and drive RTL-to-GDSII implementation for advanced nodes (sub-16nm to 3nm). * Define and ...
Senior ASIC Physical Design Engineer
Austin, TX · On-site
$165K - $241K/yr
Your Impact As a Physical Design Engineer, you will play a key role in the full RTL-to-GDSII ... Own and drive RTL-to-GDSII implementation for advanced nodes (sub-16nm to 3nm). * Define and ...
Senior CPU RTL Design Engineer - Power Management
Austin, TX · On-site
$164K - $269K/yr
As a Senior CPU RTL Design Engineer - Power Management , you will play a critical role in designing and delivering CPU microarchitectures with strong emphasis on power management and energy-efficient ...
Senior CPU RTL Design Engineer - Power Management
Austin, TX · On-site
$164K - $269K/yr
As a Senior CPU RTL Design Engineer - Power Management , you will play a critical role in designing and delivering CPU microarchitectures with strong emphasis on power management and energy-efficient ...
FE RTL Infrastructure - CAD Engineer
Austin, TX · On-site
$164K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
FE RTL Infrastructure - CAD Engineer
Austin, TX · On-site
$164K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
Design Engineer III
Austin, TX · On-site
$120K/yr
Design Engineer III ONSITE- US: TX- Austin OR Sunnyvale office (2nd option) Salary 140 to 145K ... Minimum Qualifications Demonstrated experience with RTL-to-GDSII design flow usage and development ...
Quick apply
Design Engineer III
Austin, TX · On-site
$120K/yr
Design Engineer III ONSITE- US: TX- Austin OR Sunnyvale office (2nd option) Salary 140 to 145K ... Minimum Qualifications Demonstrated experience with RTL-to-GDSII design flow usage and development ...
ASIC Design Engineer
Austin, TX · On-site
$130 - $210/hr
We're looking for ASIC design engineers to contribute to and own blocks in the development of the A-0 and A-1 wafer products, across both the XPU, memory chiplet and other dies on the wafer. Ideal ...
Posted today
ASIC Design Engineer
Austin, TX · On-site
$130 - $210/hr
We're looking for ASIC design engineers to contribute to and own blocks in the development of the A-0 and A-1 wafer products, across both the XPU, memory chiplet and other dies on the wafer. Ideal ...
Posted today
The clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible ... Experience in RTL design (Verilog), verification and logic synthesis. * Strong coding skills in ...
The clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible ... Experience in RTL design (Verilog), verification and logic synthesis. * Strong coding skills in ...
Digital/RTL IC Design Engineer
Austin, TX · On-site
$134K/yr
Digital Design Engineer focusing on high-performance analog-to-digital and digital-to-analog converters. Job responsibilities include RTL design, verification, behavioral modelling, support and ...
Quick apply
Digital/RTL IC Design Engineer
Austin, TX · On-site
$134K/yr
Digital Design Engineer focusing on high-performance analog-to-digital and digital-to-analog converters. Job responsibilities include RTL design, verification, behavioral modelling, support and ...
Temporary Asic Rtl Design Engineer information
See Leander, TX salary details
$89.8K - $99.2K
16% of jobs
$99.2K - $108.6K
3% of jobs
$108.6K - $118K
4% of jobs
$120.7K is the 25th percentile. Wages below this are outliers.
$118K - $127.3K
6% of jobs
The median wage is $133.2K / yr.
$127.3K - $136.7K
33% of jobs
$136.7K - $146.1K
3% of jobs
$146.1K - $155.5K
2% of jobs
$161.7K is the 75th percentile. Wages above this are outliers.
$155.5K - $164.9K
12% of jobs
$164.9K - $174.3K
5% of jobs
$174.3K - $183.6K
4% of jobs
$183.6K - $193K
12% of jobs
$89.8K
$143.5K
$193K
How much do temporary asic rtl design engineer jobs pay per year?
As of Aug 10, 2026, the average yearly pay for temporary asic rtl design engineer in Leander, TX is $143,513.00, according to ZipRecruiter salary data. Most workers in this role earn between $125,600.00 and $172,000.00 per year, depending on experience, location, and employer.
What is the difference between Temporary Asic Rtl Design Engineer vs Temporary FPGA Design Engineer?
| Aspect | Temporary Asic Rtl Design Engineer | Temporary FPGA Design Engineer |
|---|---|---|
| Primary Focus | Designing RTL code for ASIC chips | Designing FPGA logic and configurations |
| Skills & Certifications | Verilog/VHDL, ASIC design flow, simulation tools | Verilog/VHDL, FPGA development tools, synthesis |
| Work Environment | Semiconductor companies, ASIC design teams | FPGA development labs, prototyping environments |
| Industry Usage | Used in high-volume chip manufacturing | Used for prototyping, testing, and low-volume products |
Both roles involve RTL design using Verilog or VHDL, but the Temporary Asic Rtl Design Engineer focuses on ASIC chip development, while the Temporary FPGA Design Engineer specializes in FPGA-based prototyping and testing. The choice depends on whether the project aims for mass production or flexible, rapid development.
What are the most commonly searched types of Asic Rtl Design Engineer jobs in Leander, TX? The most popular types of Asic Rtl Design Engineer jobs in Leander, TX are:
What are popular job titles related to Temporary Asic Rtl Design Engineer jobs in Leander, TX? For Temporary Asic Rtl Design Engineer jobs in Leander, TX, the most frequently searched job titles are:
What cities near Leander, TX are hiring for Temporary Asic Rtl Design Engineer jobs? Cities near Leander, TX with the most Temporary Asic Rtl Design Engineer job openings:
Full-time
Re-posted 15 days ago
Cadence Design Systems rating
9.0
Based on 5 frontline employees who took The Breakroom Quiz
33rd of 242 rated software companies
Job description
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Cadence Solutions (North America) team is looking for an experienced candidate to lead Front End Design projects. This is a challenging and rewarding opportunity is for a highly motivated engineer with a passion for innovation and a proven track record of success in the semiconductor industry.
This is a leadership role where you will be responsible for:
Technical Leadership:
Guide and mentor a team of RTL design engineers, fostering a collaborative and innovative environment.
Design & Microarchitecture:
Define and develop microarchitectural features for IPs and subsystems, ensuring they meet PPA goals.
RTL Development:
Write, debug, and optimize RTL code in Verilog, SystemVerilog, or VHDL to create complex digital logic.
Verification & Signoff:
Oversee pre-silicon verification activities, including Lint, Clock Domain Crossing (CDC), Formal Verification (FV), and other quality checks.
Collaboration:
Work closely with cross-functional teams, including Design Verification (DV), Physical Design (PD), Architecture, and firmware engineers, to ensure successful delivery.
Qualifications:
*10+ years of Front End design and/or verification with a BS/MS Engineering or Computer Sciences
*Proven experience in leading and managing complex engineering projects
*Rich experience in IP creation and/or SoC and IP (CPU, Memory, Interface) integration
*Expert in RTL design (Verilog), simulators debuggers
*Hands on Experience in Synthesis, SDC creation and support PD and STA teams.
*Experience in driving results in multi-disciplinary organization
Desirable:
A Self-motivated person with good communication and design management skills
Experience with Cadence front end toolset
We're doing work that matters. Help us solve what others can't.
We're doing work that matters. Help us solve what others can't.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Cadence Solutions (North America) team is looking for an experienced candidate to lead Front End Design projects. This is a challenging and rewarding opportunity is for a highly motivated engineer with a passion for innovation and a proven track record of success in the semiconductor industry.
This is a leadership role where you will be responsible for:
Technical Leadership:
Guide and mentor a team of RTL design engineers, fostering a collaborative and innovative environment.
Design & Microarchitecture:
Define and develop microarchitectural features for IPs and subsystems, ensuring they meet PPA goals.
RTL Development:
Write, debug, and optimize RTL code in Verilog, SystemVerilog, or VHDL to create complex digital logic.
Verification & Signoff:
Oversee pre-silicon verification activities, including Lint, Clock Domain Crossing (CDC), Formal Verification (FV), and other quality checks.
Collaboration:
Work closely with cross-functional teams, including Design Verification (DV), Physical Design (PD), Architecture, and firmware engineers, to ensure successful delivery.
Qualifications:
*10+ years of Front End design and/or verification with a BS/MS Engineering or Computer Sciences
*Proven experience in leading and managing complex engineering projects
*Rich experience in IP creation and/or SoC and IP (CPU, Memory, Interface) integration
*Expert in RTL design (Verilog), simulators debuggers
*Hands on Experience in Synthesis, SDC creation and support PD and STA teams.
*Experience in driving results in multi-disciplinary organization
Desirable:
A Self-motivated person with good communication and design management skills
Experience with Cadence front end toolset
We're doing work that matters. Help us solve what others can't.
We're doing work that matters. Help us solve what others can't.
About Cadence Design Systems
Sourced by ZipRecruiter
Industry
Software development
Company size
5,001 - 10,000 Employees
Headquarters location
San Jose, CA, US
Year founded
1988