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Temporary Asic Rtl Design Engineer Jobs in Grapevine, TX

Glow Networks

RTL Design Engineer

Dallas, TX · On-site

RTL Design Engineer Location: Santa Clara, CA/Remote Minimum 10 years of strong experience in Digital design at RTL level using Verilog/System Verilog Experience in developing micro architectural ...

Purple Hires Inc

Lead ASIC DFT Engineer

Plano, TX · Remote

... Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for ... Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to ...

Micron Technology

HBM Sr RTL Engineer

Richardson, TX · On-site

As an SoC Design Engineer , you will be part of the Heterogeneous Integration Group (HIG ... Design and implement RTL for SoC-level blocks and subsystems used in HBM logic die. * Integrate ...

Glow Networks

RTL Engineer

Dallas, TX · On-site

The RTL Engineer performs detailed block design from system requirements and evolving specifications. Perform RTL coding, Lint checks, CDC tests, creating timing constraint file. Working closely with ...

Micron

HBM Sr RTL Engineer

Richardson, TX

As an SoC Design Engineer , you will be part of the Heterogeneous Integration Group (HIG ... Design and implement RTL for SoClevel blocks and subsystems used in HBM logic die. * Integrate ...

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All JobsTemporary Asic Rtl Design Engineer JobsTemporary Asic Rtl Design Engineer Jobs in Grapevine, TX

Temporary Asic Rtl Design Engineer information

See Grapevine, TX salary details

$86.8K

$138.8K

$186.6K

How much do temporary asic rtl design engineer jobs pay per year?

As of Jun 21, 2026, the average yearly pay for temporary asic rtl design engineer in Grapevine, TX is $138,763.00, according to ZipRecruiter salary data. Most workers in this role earn between $121,500.00 and $166,300.00 per year, depending on experience, location, and employer.

What is the difference between Temporary Asic Rtl Design Engineer vs Temporary FPGA Design Engineer?

AspectTemporary Asic Rtl Design EngineerTemporary FPGA Design Engineer
Primary FocusDesigning RTL code for ASIC chipsDesigning FPGA logic and configurations
Skills & CertificationsVerilog/VHDL, ASIC design flow, simulation toolsVerilog/VHDL, FPGA development tools, synthesis
Work EnvironmentSemiconductor companies, ASIC design teamsFPGA development labs, prototyping environments
Industry UsageUsed in high-volume chip manufacturingUsed for prototyping, testing, and low-volume products

Both roles involve RTL design using Verilog or VHDL, but the Temporary Asic Rtl Design Engineer focuses on ASIC chip development, while the Temporary FPGA Design Engineer specializes in FPGA-based prototyping and testing. The choice depends on whether the project aims for mass production or flexible, rapid development.

What cities near Grapevine, TX are hiring for Temporary Asic Rtl Design Engineer jobs? Cities near Grapevine, TX with the most Temporary Asic Rtl Design Engineer job openings:
Temporary Asic Rtl Design Engineer jobs near you
RTL Design Engineer

RTL Design Engineer

Glow Networks

Dallas, TX • On-site

Full-time

Posted 9 days ago

Job description

RTL Design Engineer
Location: Santa Clara, CA/Remote
Minimum 10 years of strong experience in Digital design at RTL level using Verilog/System Verilog
Experience in developing micro architectural document from requirements specifications
Experience developing designs from scratch
Experience applying linting and other (QC) quality checking and basic verification of designs.
Experience supporting SoC designers in integration as needed
Strong communication and collaboration skills
Preferred:
-Desirable but not essential experience: DMA, memory controller, MIPI DSI/CSI, data and control path pipeline design, interconnect and AMBA interfaces.
- Candidate with design automation, scripting experience (Python) is preferrable
• Develop HW architecture from specification documents.
• Take complete responsibilities include writing RTL code for IP development/RTL integration, checking the code for Lint/CDC issues, checking synthesizability and timing quality of the design, checking low power implementation, supporting verification team with debug and support physical design teams on timing constraints and other design topics using Verilog/System Verilog/VHDL.
• Develop and execute low power design (UPF/CPF).
• Design top level RTL, integration of blocks, clocks, resets, configuration registers, etc
• Knowledge of JESD204C block design and related design/verification experience (includes licensed IP & PHY from 3rd parties)
• Awareness of DFT concepts to be used to fix functional violation that may get introduced which including DFT structures.
• Carry out static checks including Lint/CDC (Spyglass), synthesis, LEC and STA. Debugging and fixing functional break.
• Take ownership of tasks and drive tasks to closure.

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