Temporary Asic Rtl Design Engineer Jobs in Grapevine, TX

ASIC Design Engineer

This role focuses on front-end RTL design for advanced image and video processing SoCs, working with complex CPU/GPU-style architectures and high-speed interconnects. You will design and implement Verilog/SystemVerilog blocks, contribute to functional verification, and help evolve a low-power ASIC platform that builds on existing designs and FPGA prototypes. This is a hands-on engineering position with significant ownership of block-level design, integration, and simulation.

Responsibilities

• Design and implement Verilog and SystemVerilog blocks for an image and video processing SoC.
• Work on front-end RTL design, focusing on CPU/GPU-style SoC architecture rather than backend synthesis.
• Develop and integrate block-level RTL that is self-contained, reusable, and optimized for low power and high performance.
• Perform block-level integration into the larger SoC, ensuring proper interaction with AXI interconnects and other high-speed interfaces.
• Run simulations for your own blocks and integrated designs to validate functionality and performance.
• Apply design verification and functional coverage methodologies, including UVM, to ensure robust and high-quality designs.
• Collaborate on the evolution of an existing ASIC, including adding new blocks and supporting partial reuse of existing logic.
• Support the porting of FPGA implementations to ASIC, helping to differentiate and optimize for low power and efficiency.
• Work with high-bandwidth and high-speed techniques to handle continuous streams of image and video data.
• Contribute to technical discussions on SoC/CPU/GPU architecture, interconnect strategies, and interface design.
• Document design specifications, implementation details, and verification plans to support ongoing development and future reuse.
• Participate in design reviews and provide constructive feedback to peers to maintain high engineering standards.

Essential Skills

• Experience with SoC, CPU, and GPU architectures, including AXI interconnects, high-speed interfaces, and high-bandwidth techniques.
• Preferably 5+ years of hands-on RTL design experience in industry; strong candidates with 5+ years of relevant experience will be considered.
• Strong proficiency in Verilog and SystemVerilog for complex ASIC and SoC designs.
• Proven experience with ASIC front-end design, focusing on RTL implementation rather than backend synthesis.
• Hands-on experience with design verification and functional coverage methodologies.
• Practical knowledge of UVM-based verification environments and workflows.
• Ability to design and own block-level RTL, integrate it into a larger SoC, and perform associated simulations.
• Experience image or video processing pipelines, or other high-throughput data processing systems.
• Demonstrated ability to work independently on complex technical tasks and deliver high-quality, production-ready RTL.

Additional Skills & Qualifications

• Experience working on video processing or image processing SoCs, especially with continuous data streams.
• Experience in low-power design techniques and optimization for ASIC implementations.
• Experience porting FPGA designs to ASIC, including partial reuse and new block development.
• Familiarity with high-speed, high-bandwidth interconnect design and performance optimization.
• Comfort discussing and analyzing CPU/GPU-style design trade-offs and architectural decisions.
• Experience in environments where ASIC engagements span 9 to 18 months or more.
• Ability to thrive in a fast-paced environment with surge project needs and multiple concurrent ASIC design efforts.

This is a Contract position based out of Richardson, TX.

The pay range for this position is $80.00 - $110.00/hr.

Eligibility requirements apply to some benefits and may depend on your job classification and length of employment. Benefits are subject to change and may be subject to specific elections, plan, or program terms. If eligible, the benefits available for this temporary role may include the following:
• Medical, dental & vision
• Critical Illness, Accident, and Hospital
• 401(k) Retirement Plan – Pre-tax and Roth post-tax contributions available
• Life Insurance (Voluntary Life & AD&D for the employee and dependents)
• Short and long-term disability
• Health Spending Account (HSA)
• Transportation benefits
• Employee Assistance Program
• Time Off/Leave (PTO, Vacation or Sick Leave)

This is a fully onsite position in Richardson,TX.

This position is anticipated to close on Jul 14, 2026.

About Actalent

Actalent is a global leader in engineering and sciences services and talent solutions. We help visionary companies advance their engineering and science initiatives through access to specialized experts who drive scale, innovation and speed to market. With a network of almost 20,000 consultants and 5,000 clients across the U.S., Canada, Asia and Europe, Actalent serves many of the Fortune 500. We are proud to be an Engineering News-Record (ENR) Top 500 Design Firm for our engineering design services and a ClearlyRated Best of Staffing® winner for both client and talent service.

The company is an equal opportunity employer and will consider all applications without regard to race, sex, age, color, religion, national origin, veteran status, disability, sexual orientation, gender identity, genetic information or any characteristic protected by law.

If you would like to request a reasonable accommodation, such as the modification or adjustment of the job application process or interviewing process due to a disability, please email actalentaccommodation@actalentservices.com for other accommodation options.

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