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Telecommute Asic Rtl Design Engineer Jobs in Dallas, TX

Glow Networks

RTL Design Engineer

Dallas, TX · On-site

RTL Design Engineer Location: Santa Clara, CA/Remote Minimum 10 years of strong experience in Digital design at RTL level using Verilog/System Verilog Experience in developing micro architectural ...

Glow Networks

RTL Engineer

Dallas, TX · On-site

The RTL Engineer performs detailed block design from system requirements and evolving specifications. Perform RTL coding, Lint checks, CDC tests, creating timing constraint file. Working closely with ...

InstantServe LLC

senior FGPA Engineer

Richardson, TX · On-site

$102.80K - $133.90K/yr

Proficient in RTL design (VHDL preferred) and experience with Xilinx or Intel FPGAs and development environments. * Experience in implementing signal processing functions (DSP) targeting FPGA or ASIC ...

Micron

Principal SoC Design Engineer, HBM

Richardson, TX

$123.50K - $127.10K/yr

As an SoC Design Engineer , you will be part of the Heterogeneous Integration Group (HIG ... Design and implement RTL for SoClevel blocks and subsystems used in HBM logic die. * Integrate ...

Micron

HBM SOC Design Engineer

Richardson, TX

As an HBM SOC Design Engineer, you will be responsible for the design & development of next ... You will apply your deep understanding of SOC Architecture, RTL Logic Design, IP Integration, high ...

Raytheon

Senior FPGA Design Engineer

Dallas, TX

$121.70K - $167.70K/yr

As a Senior FPGA Design Engineer you will develop FPGA designs for all major vendors and device ... FPGA/ASIC design, including VHDL and/or Verilog coding or FPGA/ASIC verification using ...

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$93K

$148.6K

$199.8K

How much do telecommute asic rtl design engineer jobs pay per year?

As of May 28, 2026, the average yearly pay for telecommute asic rtl design engineer in Dallas, TX is $148,578.00, according to ZipRecruiter salary data. Most workers in this role earn between $130,100.00 and $178,100.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a Telecommute ASIC RTL Design Engineer, and why are they important?

To thrive as a Telecommute ASIC RTL Design Engineer, you need a strong background in digital logic design, proficiency in hardware description languages like Verilog or VHDL, and typically a degree in electrical or computer engineering. Familiarity with EDA tools such as Synopsys or Cadence, as well as experience with simulation, synthesis, and debugging environments, is essential. Strong problem-solving abilities, attention to detail, and effective communication skills are crucial for collaborating remotely and ensuring design accuracy. These skills are vital to deliver complex, high-performance ASICs on schedule while working efficiently in a remote setting.

What are some common challenges faced by telecommute ASIC RTL Design Engineers, and how can they be addressed?

Telecommute ASIC RTL Design Engineers often face challenges like coordinating effectively with remote teams, ensuring version control integrity, and maintaining clear communication on project specifications. These challenges can be mitigated by utilizing robust collaboration tools, adhering to standardized documentation practices, and scheduling regular virtual meetings for design reviews. Additionally, staying proactive in seeking feedback and clarifying requirements helps ensure alignment and prevents costly design iterations.

What is a Telecommute ASIC RTL Design Engineer?

A Telecommute ASIC RTL Design Engineer is a professional who specializes in designing digital circuits at the Register Transfer Level (RTL) for Application-Specific Integrated Circuits (ASICs), while working remotely. They use hardware description languages like Verilog or VHDL to create and verify circuit designs tailored to specific applications. Their responsibilities often include developing, simulating, and optimizing digital logic, collaborating with cross-functional teams, and ensuring that the final silicon meets design specifications. Since the role is telecommute, all work is performed from a remote location using digital communication and collaboration tools.

What is the difference between Telecommute Asic Rtl Design Engineer vs Telecommute Digital IC Design Engineer?

AspectTelecommute Asic Rtl Design EngineerTelecommute Digital IC Design Engineer
CredentialsBachelor's or Master's in Electrical Engineering or Computer Engineering; experience with RTL codingBachelor's or Master's in Electrical Engineering or Computer Engineering; experience with digital circuit design
Work EnvironmentRemote, primarily designing RTL code for ASICsRemote, focusing on digital IC architecture and design
Industry UsageCommon in semiconductor and electronics companies

Both roles often require similar educational backgrounds and work remotely in the semiconductor industry. The main difference lies in their focus: RTL Design Engineers concentrate on writing RTL code for ASICs, while Digital IC Design Engineers work on broader digital circuit architecture. Candidates should choose based on their specific skills and career interests in digital design or RTL coding.

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Telecommute Asic Rtl Design Engineer jobs near you
RTL Design Engineer

RTL Design Engineer

Glow Networks

Dallas, TX • On-site

Full-time

Posted 15 days ago

Job description

RTL Design Engineer
Location: Santa Clara, CA/Remote
Minimum 10 years of strong experience in Digital design at RTL level using Verilog/System Verilog
Experience in developing micro architectural document from requirements specifications
Experience developing designs from scratch
Experience applying linting and other (QC) quality checking and basic verification of designs.
Experience supporting SoC designers in integration as needed
Strong communication and collaboration skills
Preferred:
-Desirable but not essential experience: DMA, memory controller, MIPI DSI/CSI, data and control path pipeline design, interconnect and AMBA interfaces.
- Candidate with design automation, scripting experience (Python) is preferrable
• Develop HW architecture from specification documents.
• Take complete responsibilities include writing RTL code for IP development/RTL integration, checking the code for Lint/CDC issues, checking synthesizability and timing quality of the design, checking low power implementation, supporting verification team with debug and support physical design teams on timing constraints and other design topics using Verilog/System Verilog/VHDL.
• Develop and execute low power design (UPF/CPF).
• Design top level RTL, integration of blocks, clocks, resets, configuration registers, etc
• Knowledge of JESD204C block design and related design/verification experience (includes licensed IP & PHY from 3rd parties)
• Awareness of DFT concepts to be used to fix functional violation that may get introduced which including DFT structures.
• Carry out static checks including Lint/CDC (Spyglass), synthesis, LEC and STA. Debugging and fixing functional break.
• Take ownership of tasks and drive tasks to closure.

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