Hardware Engineer
Chicago, IL ยท On-site
$127K - $168K/yr
Design and implement RTL for next-generation ASIC platforms using SystemVerilog * Contribute to architecture and design discussions for performance-critical hardware systems * Develop new ...
Chicago, IL ยท On-site
$127K - $168K/yr
Design and implement RTL for next-generation ASIC platforms using SystemVerilog * Contribute to architecture and design discussions for performance-critical hardware systems * Develop new ...
Chicago, IL ยท On-site
$127K - $168K/yr
Design and implement RTL for next-generation ASIC platforms using SystemVerilog * Contribute to architecture and design discussions for performance-critical hardware systems * Develop new ...
Chicago, IL ยท On-site
$127K - $167K/yr
Design and implement RTL for next-generation ASIC platforms using SystemVerilog * Contribute to architecture and design discussions for performance-critical hardware systems * Develop new ...
Chicago, IL ยท On-site
$127K - $167K/yr
Design and implement RTL for next-generation ASIC platforms using SystemVerilog * Contribute to architecture and design discussions for performance-critical hardware systems * Develop new ...
$127K - $167K/yr
Design and implement RTL for next-generation ASIC platforms using SystemVerilog * Contribute to architecture and design discussions for performance-critical hardware systems * Develop new ...
$127K - $167K/yr
Design and implement RTL for next-generation ASIC platforms using SystemVerilog * Contribute to architecture and design discussions for performance-critical hardware systems * Develop new ...
Batavia, IL ยท On-site
$70K - $93K/yr
We are looking for a Junior ASIC Design Engineer to lead and contribute to research activities and engineering work focused on developing custom instrumentation for extreme radiation and/or cryogenic ...
Batavia, IL ยท On-site
$70K - $93K/yr
We are looking for a Junior ASIC Design Engineer to lead and contribute to research activities and engineering work focused on developing custom instrumentation for extreme radiation and/or cryogenic ...
... ASIC design experience. * Sr. Principal FPGA Design Engineer (Level 4): Bachelors' degree in ... Proficient in FPGA design flow including items such as RTL/gate level simulation, synthesis, place ...
... ASIC design experience. * Sr. Principal FPGA Design Engineer (Level 4): Bachelors' degree in ... Proficient in FPGA design flow including items such as RTL/gate level simulation, synthesis, place ...
... ASIC design experience. * Sr. Principal FPGA Design Engineer (Level 4): Bachelors' degree in ... Proficient in FPGA design flow including items such as RTL/gate level simulation, synthesis, place ...
... ASIC design experience. * Sr. Principal FPGA Design Engineer (Level 4): Bachelors' degree in ... Proficient in FPGA design flow including items such as RTL/gate level simulation, synthesis, place ...
Vernon Hills, IL ยท On-site
$150 - $180/hr
... Engineer to join our VHDL Department ... In this role, you will oversee definition, design, verification, and documentation for FPGA/ASIC ...
New
Vernon Hills, IL ยท On-site
$150 - $180/hr
... Engineer to join our VHDL Department ... In this role, you will oversee definition, design, verification, and documentation for FPGA/ASIC ...
New
Vernon Hills, IL ยท On-site
$150 - $180/hr
... Engineer to join our VHDLDepartment ... In this role, you will oversee definition, design, verification, and documentation forFPGA/ASIC ...
New
Vernon Hills, IL ยท On-site
$150 - $180/hr
... Engineer to join our VHDLDepartment ... In this role, you will oversee definition, design, verification, and documentation forFPGA/ASIC ...
New
... Engineering, or related fields * 12+ years of experience in digital design of high-speed SerDes, PHY, or transceiver IPs with proven tapeout experience at 112G PAM4 or higher data rates * Strong RTL ...
Quick apply
... Engineering, or related fields * 12+ years of experience in digital design of high-speed SerDes, PHY, or transceiver IPs with proven tapeout experience at 112G PAM4 or higher data rates * Strong RTL ...
Vernon Hills, IL ยท On-site
$150 - $180/hr
... Engineer to join our VHDL Department ... In this role, you will oversee definition, design, verification, and documentation for FPGA/ASIC ...
Vernon Hills, IL ยท On-site
$150 - $180/hr
... Engineer to join our VHDL Department ... In this role, you will oversee definition, design, verification, and documentation for FPGA/ASIC ...
$138K - $142K/yr
As an Eliyan Sr Staff / Principal Physical Design Engineer, you will be working at a fast-paced ... You will drive the development of cutting-edge ASICs from RTL to GDSII. You will work with a cross ...
Quick apply
$138K - $142K/yr
As an Eliyan Sr Staff / Principal Physical Design Engineer, you will be working at a fast-paced ... You will drive the development of cutting-edge ASICs from RTL to GDSII. You will work with a cross ...
Mossville, IL ยท On-site
$113K - $131K/yr
Telecommuting: 2 days/week. Up to 10% domestic travel to Caterpillar facilities to support controls ... Design Engineer / R0000379543 ] . #LI-DNI Visa Sponsorship is not available for this position.
Mossville, IL ยท On-site
$113K - $131K/yr
Telecommuting: 2 days/week. Up to 10% domestic travel to Caterpillar facilities to support controls ... Design Engineer / R0000379543 ] . #LI-DNI Visa Sponsorship is not available for this position.
$104K - $136K/yr
Interface with Front End RTL design teams and Back End Verification teams Position Requirements/Qualifications:
$104K - $136K/yr
Interface with Front End RTL design teams and Back End Verification teams Position Requirements/Qualifications:
$136K - $253K/yr
Interface with Front End RTL design teams and Back End Verification teams Position Requirements/Qualifications:
$136K - $253K/yr
Interface with Front End RTL design teams and Back End Verification teams Position Requirements/Qualifications:
Loves Park, IL ยท On-site
$37.78 - $48/hr
Electrical Design Engineer Department: Engineering - Electrical Reports to: Electrical Engineering ... Telecommuting up to 2 days a week, Flex work schedule, Identity Theft Protection
Quick apply
Loves Park, IL ยท On-site
$37.78 - $48/hr
Electrical Design Engineer Department: Engineering - Electrical Reports to: Electrical Engineering ... Telecommuting up to 2 days a week, Flex work schedule, Identity Theft Protection
... RTL design and verification through synthesis, place-and-route, timing, power, signoff, and ... Define and report KPIs - cycle-time reduction, engineer-hours saved, iteration count, first-pass ...
... RTL design and verification through synthesis, place-and-route, timing, power, signoff, and ... Define and report KPIs - cycle-time reduction, engineer-hours saved, iteration count, first-pass ...
ABOUT THE ROLE As a Sr Staff / Principal CAD & Design Methodology Engineer , you will be the technical architect of RTL-to-GDSII flows and digital design infrastructure for advanced SoC products. You ...
Quick apply
ABOUT THE ROLE As a Sr Staff / Principal CAD & Design Methodology Engineer , you will be the technical architect of RTL-to-GDSII flows and digital design infrastructure for advanced SoC products. You ...
As an Eliyan Principal Physical Design Engineer, you will be working at a fast-paced early-stage ... You will drive the development of cutting-edge ASICs from RTL to GDSII. You will work with a cross ...
Quick apply
As an Eliyan Principal Physical Design Engineer, you will be working at a fast-paced early-stage ... You will drive the development of cutting-edge ASICs from RTL to GDSII. You will work with a cross ...
Chicago, IL ยท On-site
Our team spans trading, engineering, and business operations, working together to build and support ... Design, implement, and verify RTL logic in Verilog or SystemVerilog targeting ultra-low-latency ...
Chicago, IL ยท On-site
Our team spans trading, engineering, and business operations, working together to build and support ... Design, implement, and verify RTL logic in Verilog or SystemVerilog targeting ultra-low-latency ...
Mentor engineers on protocol implementation, timing constraints, and hierarchical design ... Extremely knowledgeable on RTL-to-GDSII flows, limitations, and flexibilities to improve ...
Quick apply
Mentor engineers on protocol implementation, timing constraints, and hierarchical design ... Extremely knowledgeable on RTL-to-GDSII flows, limitations, and flexibilities to improve ...
| Aspect | Telecommute Asic Rtl Design Engineer | Telecommute Digital IC Design Engineer |
|---|---|---|
| Credentials | Bachelor's or Master's in Electrical Engineering or Computer Engineering; experience with RTL coding | Bachelor's or Master's in Electrical Engineering or Computer Engineering; experience with digital circuit design |
| Work Environment | Remote, primarily designing RTL code for ASICs | Remote, focusing on digital IC architecture and design |
| Industry Usage | Common in semiconductor and electronics companies |
Both roles often require similar educational backgrounds and work remotely in the semiconductor industry. The main difference lies in their focus: RTL Design Engineers concentrate on writing RTL code for ASICs, while Digital IC Design Engineers work on broader digital circuit architecture. Candidates should choose based on their specific skills and career interests in digital design or RTL coding.
The most popular types of Asic Rtl Design Engineer jobs in Illinois are:
Cities in Illinois with the most Telecommute Asic Rtl Design Engineer job openings: