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Telecommute Asic Rtl Design Engineer Jobs in Illinois

Tanisha Systems, Inc.

ASIC DFT Engineer

Rockford, IL · On-site

Title - Lead ASIC DFT Engineer Location - Remote (must be aligned with PST time zone) Type :- */W2 ... Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to ...

IMC

Hardware Engineer

Chicago, IL · On-site

$127K - $168K/yr

Design and implement RTL for next-generation ASIC platforms using SystemVerilog * Contribute to architecture and design discussions for performance-critical hardware systems * Develop new ...

IMC

Hardware Engineer

Chicago, IL · On-site

$127K - $167K/yr

Design and implement RTL for next-generation ASIC platforms using SystemVerilog * Contribute to architecture and design discussions for performance-critical hardware systems * Develop new ...

IMC

Hardware Engineer

Chicago, IL

$127K - $167K/yr

Design and implement RTL for next-generation ASIC platforms using SystemVerilog * Contribute to architecture and design discussions for performance-critical hardware systems * Develop new ...

Fermilab

Jr. ASIC Design Engineer

Batavia, IL · On-site

$70K - $93K/yr

We are looking for a Junior ASIC Design Engineer to lead and contribute to research activities and engineering work focused on developing custom instrumentation for extreme radiation and/or cryogenic ...

Eliyan

Digital - SerDes Digital Design Lead

Mundelein, IL · On-site

$138K/yr

... Engineering, or related fields * 12+ years of experience in digital design of high-speed SerDes, PHY, or transceiver IPs with proven tapeout experience at 112G PAM4 or higher data rates * Strong RTL ...

Apply Early

Stefanini

$121K - $167K/yr

Stefanini is looking for FPGA Design Engineer with Radio experience (Onsite Role) in Ottawa ... Working with 4G/5G Radios. 7+ years of experience Heavy System Verilog and RTL experience. They DO ...

Eliyan

PD - IP Lead - Sr Staff, Physical Design

Mundelein, IL

$138K - $142K/yr

As an Eliyan Sr Staff / Principal Physical Design Engineer, you will be working at a fast-paced ... You will drive the development of cutting-edge ASICs from RTL to GDSII. You will work with a cross ...

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Caterpillar

Design Engineer

Mossville, IL · On-site

$113K - $131K/yr

Telecommuting: 2 days/week. Up to 10% domestic travel to Caterpillar facilities to support controls ... Design Engineer / R0000379543 ] . #LI-DNI Visa Sponsorship is not available for this position.

Aqua Aerobic

Controls Design Engineer

Loves Park, IL · On-site

$37.78 - $48/hr

Electrical Design Engineer Department: Engineering - Electrical Reports to: Electrical Engineering ... Telecommuting up to 2 days a week, Flex work schedule, Identity Theft Protection

Apply Early

Akuna Capital

Senior FPGA Engineer

Chicago, IL

$145K/yr

Develop and maintain RTL in Verilog/SystemVerilog * Write and maintain verification environments ... or ASIC digital logic design - network traffic experience a strong plus * Deep Verilog ...

Akuna Capital

Senior FPGA Engineer

Chicago, IL · On-site

$145K/yr

Develop and maintain RTL in Verilog/SystemVerilog * Write and maintain verification environments ... or ASIC digital logic design - network traffic experience a strong plus * Deep Verilog ...

Eliyan

PD - Principal, Physical Design

Mundelein, IL · On-site

As an Eliyan Principal Physical Design Engineer, you will be working at a fast-paced early-stage ... You will drive the development of cutting-edge ASICs from RTL to GDSII. You will work with a cross ...

Apply Early

Edgehog Trading

Junior FPGA Developer

Chicago, IL · On-site

Our team spans trading, engineering, and business operations, working together to build and support ... Design, implement, and verify RTL logic in Verilog or SystemVerilog targeting ultra-low-latency ...

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All JobsTelecommute Asic Rtl Design Engineer JobsTelecommute Asic Rtl Design Engineer Jobs in Illinois

Telecommute Asic Rtl Design Engineer information

What are some common challenges faced by telecommute ASIC RTL Design Engineers, and how can they be addressed?

Telecommute ASIC RTL Design Engineers often face challenges like coordinating effectively with remote teams, ensuring version control integrity, and maintaining clear communication on project specifications. These challenges can be mitigated by utilizing robust collaboration tools, adhering to standardized documentation practices, and scheduling regular virtual meetings for design reviews. Additionally, staying proactive in seeking feedback and clarifying requirements helps ensure alignment and prevents costly design iterations.

What are the key skills and qualifications needed to thrive as a Telecommute ASIC RTL Design Engineer, and why are they important?

To thrive as a Telecommute ASIC RTL Design Engineer, you need a strong background in digital logic design, proficiency in hardware description languages like Verilog or VHDL, and typically a degree in electrical or computer engineering. Familiarity with EDA tools such as Synopsys or Cadence, as well as experience with simulation, synthesis, and debugging environments, is essential. Strong problem-solving abilities, attention to detail, and effective communication skills are crucial for collaborating remotely and ensuring design accuracy. These skills are vital to deliver complex, high-performance ASICs on schedule while working efficiently in a remote setting.

What is a Telecommute ASIC RTL Design Engineer?

A Telecommute ASIC RTL Design Engineer is a professional who specializes in designing digital circuits at the Register Transfer Level (RTL) for Application-Specific Integrated Circuits (ASICs), while working remotely. They use hardware description languages like Verilog or VHDL to create and verify circuit designs tailored to specific applications. Their responsibilities often include developing, simulating, and optimizing digital logic, collaborating with cross-functional teams, and ensuring that the final silicon meets design specifications. Since the role is telecommute, all work is performed from a remote location using digital communication and collaboration tools.

What is the difference between Telecommute Asic Rtl Design Engineer vs Telecommute Digital IC Design Engineer?

AspectTelecommute Asic Rtl Design EngineerTelecommute Digital IC Design Engineer
CredentialsBachelor's or Master's in Electrical Engineering or Computer Engineering; experience with RTL codingBachelor's or Master's in Electrical Engineering or Computer Engineering; experience with digital circuit design
Work EnvironmentRemote, primarily designing RTL code for ASICsRemote, focusing on digital IC architecture and design
Industry UsageCommon in semiconductor and electronics companies

Both roles often require similar educational backgrounds and work remotely in the semiconductor industry. The main difference lies in their focus: RTL Design Engineers concentrate on writing RTL code for ASICs, while Digital IC Design Engineers work on broader digital circuit architecture. Candidates should choose based on their specific skills and career interests in digital design or RTL coding.

What are the most commonly searched types of Asic Rtl Design Engineer jobs in Illinois? The most popular types of Asic Rtl Design Engineer jobs in Illinois are:
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Telecommute Asic Rtl Design Engineer jobs near you
ASIC DFT Engineer

ASIC DFT Engineer

Tanisha Systems, Inc.

Rockford, IL • On-site

Other

Posted 15 days ago

Job description

Title - Lead ASIC DFT Engineer
Location – Remote (must be aligned with PST time zone)
Type :- */W2
Experience
10+ years of hands-on experience in ASIC Design-for-Test (DFT)
Role Summary
We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues.
The ideal candidate will have strong hands-on expertise in DFT fundamentals, fault models, test coverage, diagnosis, and debug, as well as the ability to evaluate and adopt emerging DFT methodologies and architecture schemes to improve robustness, quality, and yield.
Key Responsibilities
  • Lead DFT architecture, implementation, verification, and sign-off for complex ASIC and SoC designs.
  • Drive scan architecture, scan insertion, scan chain stitching, and scan compression workflows to achieve high coverage and robust testability.
  • Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon bring-up phases.
  • Perform DFT debug, failure analysis, root-cause investigation, and fault coverage closure for complex silicon issues.
  • Develop and validate DFT constraints, including DFT SDC, timing checks, and DFT-specific timing analysis.
  • Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to resolve integration and implementation issues.
  • Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug.
  • Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration.
  • Review RTL, synthesis, LEC, and physical design impacts on DFT implementation and test quality.
  • Act as a technical escalation point for advanced DFT and post-silicon debug issues.
  • Mentor junior and mid-level DFT engineers and promote best practices in DFT methodology and automation.
  • Develop scripts and automation using TCL, PERL, or Python to improve flow efficiency and debug productivity.
Required Skills & Qualifications
  • Strong hands-on experience in ASIC DFT with end-to-end ownership.
  • Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.
  • Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.
  • Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.
  • Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.
  • Experience with MBIST implementation and verification; SMS experience preferred.
  • Experience with scan architecture and scan chain stitching; Tessent/SSN experience preferred.
  • Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and physical design implementation.
  • Proven post-silicon debug and silicon bring-up experience.
  • Exposure to large SoC designs, hierarchical DFT flows, and multi-domain integration challenges.
  • Strong communication skills and the ability to work independently with minimal ramp-up.
Preferred Experience
  • MBIST post-silicon validation.
  • ATPG simulations and fault coverage debug.
  • DFT RTL, DFD, DFT verification, and IP-level DFT integration.
  • DFT SDC creation and DFT timing closure support.
  • Boundary scan, iJTAG, SSN, and design-for-debug methodologies.
  • TCL/PERL scripting for DFT automation, reporting, and debug.
  • Experience working across multiple ASIC technology nodes and complex product development cycles.
  • Familiarity with yield learning, diagnosis, and manufacturing test optimization.
Regards
Nirdosh Singh
Sr. Account Manager | Tanisha Systems Inc.
Phone: 732-377-3299 x 599
Email: nirdosh@tanishasystems.com
Web: www.tanishasystems.com
99 Wood Ave South, Suite # 308, Iselin, NJ 08830
LinkedIn :- https://www.linkedin.com/in/nirdosh-soami-rajput/
About Tanisha Systems, Inc.
Tanisha Systems, founded in 2002 in Massachusetts-*, is a leading provider of Custom Application Development and end-to-end IT Services to clients globally. We use a client-centric engagement model that combines local on-site and off-site resources with the cost, global expertise and quality advantages of off-shore operations. We deliver Custom Application Development, Application Modernization, Business Process Outsourcing and Professional IT Services from office locations in * and *.
Tanisha Systems services clients in Government, Banking & Financial Markets, Insurance, Healthcare, Retail & Consumer Goods, Energy & Utilities, Life Sciences, Telecom, Manufacturing and Transportation Industries around the globe. Our engagement model provides a flexible operational environment that empowers our clients with the right levels of control.
Want to read more about Tanisha Systems? Visit us at www.tanishasystems.com
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