Join a world-class team of scientists, engineers, and business professionals to advance the ... Perform hands-on ASIC design including microarchitecture, RTL development, testing, and integration.
Join a world-class team of scientists, engineers, and business professionals to advance the ... Perform hands-on ASIC design including microarchitecture, RTL development, testing, and integration.
Principal ASIC Design Engineer
$180K - $220K/yr
Perform hands-on ASIC design including microarchitecture, RTL development, testing, and integration ... MS or PhD in Electrical Engineering or a related field. * 10+ years of post-degree experience in ...
Principal ASIC Design Engineer
$180K - $220K/yr
Perform hands-on ASIC design including microarchitecture, RTL development, testing, and integration ... MS or PhD in Electrical Engineering or a related field. * 10+ years of post-degree experience in ...
Principal ASIC Design Engineer
$180K - $220K/yr
Perform hands-on ASIC design including microarchitecture, RTL development, testing, and integration ... MS or PhD in Electrical Engineering or a related field. * 10+ years of post-degree experience in ...
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Principal ASIC Design Engineer
$180K - $220K/yr
Perform hands-on ASIC design including microarchitecture, RTL development, testing, and integration ... MS or PhD in Electrical Engineering or a related field. * 10+ years of post-degree experience in ...
... design and space. Key activities you will accomplish in this role: Architect and implement ASIC ... ASIC RTL to emulation and FPGA-based platforms Develop and execute validation plans for complex ...
... design and space. Key activities you will accomplish in this role: Architect and implement ASIC ... ASIC RTL to emulation and FPGA-based platforms Develop and execute validation plans for complex ...
... design and space. Key activities you will accomplish in this role: Architect and implement ASIC ... ASIC RTL to emulation and FPGA-based platforms Develop and execute validation plans for complex ...
... design and space. Key activities you will accomplish in this role: Architect and implement ASIC ... ASIC RTL to emulation and FPGA-based platforms Develop and execute validation plans for complex ...
Senior Engineer, Digital Design Engineering
Colorado Springs, CO · On-site
$112.02K - $166.67K/yr
... RTL, Standard cells, and similar approaches as necessary for both mixed signal ASIC and FPGA ... Partial telecommute benefit (2 days/week work from home). Requirements: Must have a Master's degree ...
Senior Engineer, Digital Design Engineering
Colorado Springs, CO · On-site
$112.02K - $166.67K/yr
... RTL, Standard cells, and similar approaches as necessary for both mixed signal ASIC and FPGA ... Partial telecommute benefit (2 days/week work from home). Requirements: Must have a Master's degree ...
Senior Engineer, Digital Design Engineering
Colorado Springs, CO · On-site
$112.02K - $166.67K/yr
... RTL, Standard cells, and similar approaches as necessary for both mixed signal ASIC and FPGA ... Partial telecommute benefit (2 days/week work from home). Requirements: Must have a Master's degree ...
Senior Engineer, Digital Design Engineering
Colorado Springs, CO · On-site
$112.02K - $166.67K/yr
... RTL, Standard cells, and similar approaches as necessary for both mixed signal ASIC and FPGA ... Partial telecommute benefit (2 days/week work from home). Requirements: Must have a Master's degree ...
Senior Engineer, Digital Design Engineering
$112.02K - $166.67K/yr
... RTL, Standard cells, and similar approaches as necessary for both mixed signal ASIC and FPGA ... Partial telecommute benefit (2 days/week work from home). Requirements: Must have a Master's degree ...
Senior Engineer, Digital Design Engineering
$112.02K - $166.67K/yr
... RTL, Standard cells, and similar approaches as necessary for both mixed signal ASIC and FPGA ... Partial telecommute benefit (2 days/week work from home). Requirements: Must have a Master's degree ...
ASIC Digital Design Engineer
Colorado Springs, CO · On-site
$134K/yr
IP integration, RTL design, and verification of digital and mixed-signal ASICs from the block ... an ASIC * Fluency with object-oriented programming * Strong teamwork and written/verbal ...
ASIC Digital Design Engineer
Colorado Springs, CO · On-site
$134K/yr
IP integration, RTL design, and verification of digital and mixed-signal ASICs from the block ... an ASIC * Fluency with object-oriented programming * Strong teamwork and written/verbal ...
ASIC Digital Design Engineer
Colorado Springs, CO · On-site
$134K/yr
IP integration, RTL design, and verification of digital and mixed-signal ASICs from the block ... an ASIC * Fluency with object-oriented programming * Strong teamwork and written/verbal ...
ASIC Digital Design Engineer
Colorado Springs, CO · On-site
$134K/yr
IP integration, RTL design, and verification of digital and mixed-signal ASICs from the block ... an ASIC * Fluency with object-oriented programming * Strong teamwork and written/verbal ...
... design and space. Key activities you will accomplish in this role: • Architect and implement ASIC ... Map ASIC RTL to emulation and FPGA-based platforms • Develop and execute validation plans for ...
... design and space. Key activities you will accomplish in this role: • Architect and implement ASIC ... Map ASIC RTL to emulation and FPGA-based platforms • Develop and execute validation plans for ...
ASIC Digital Physical Design Manager
Colorado Springs, CO · On-site
$134K - $138K/yr
Our team of senior engineers has delivered generations of innovation across ASIC and product ... Coordinate closely with RTL/design, DFT/test, packaging, and systems teams to ensure clean handoffs ...
ASIC Digital Physical Design Manager
Colorado Springs, CO · On-site
$134K - $138K/yr
Our team of senior engineers has delivered generations of innovation across ASIC and product ... Coordinate closely with RTL/design, DFT/test, packaging, and systems teams to ensure clean handoffs ...
ASIC Physical Design Manager
Colorado Springs, CO · On-site
$134K - $138K/yr
Our team of senior engineers has delivered generations of innovation across ASIC and product ... Coordinate closely with RTL/design, DFT/test, packaging, and systems teams to ensure clean handoffs ...
ASIC Physical Design Manager
Colorado Springs, CO · On-site
$134K - $138K/yr
Our team of senior engineers has delivered generations of innovation across ASIC and product ... Coordinate closely with RTL/design, DFT/test, packaging, and systems teams to ensure clean handoffs ...
Design Engineer
Fort Collins, CO · On-site
$60.20K - $96.30K/yr
Join a world-class engineering group developing custom CMOS ASICs for cutting-edge AI, Cellular ... Gain exposure to the complete ASIC design cycle - from RTL to GDSII and silicon bring-up.
Design Engineer
Fort Collins, CO · On-site
$60.20K - $96.30K/yr
Join a world-class engineering group developing custom CMOS ASICs for cutting-edge AI, Cellular ... Gain exposure to the complete ASIC design cycle - from RTL to GDSII and silicon bring-up.
Design Engineer
$60.20K - $96.30K/yr
Join a world-class engineering group developing custom CMOS ASICs for cutting-edge AI, Cellular ... Gain exposure to the complete ASIC design cycle - from RTL to GDSII and silicon bring-up.
Design Engineer
$60.20K - $96.30K/yr
Join a world-class engineering group developing custom CMOS ASICs for cutting-edge AI, Cellular ... Gain exposure to the complete ASIC design cycle - from RTL to GDSII and silicon bring-up.
Digital ASIC Design Manager
Colorado Springs, CO · On-site
$134K/yr
We are seeking a Digital Design ASIC R&D Manager to lead and grow this capability within our ASIC ... RTL designers, and verification engineers; establish clear technical expectations and a culture of ...
Digital ASIC Design Manager
Colorado Springs, CO · On-site
$134K/yr
We are seeking a Digital Design ASIC R&D Manager to lead and grow this capability within our ASIC ... RTL designers, and verification engineers; establish clear technical expectations and a culture of ...
ASIC Engineer 2
$143 - $222.01/hr
Define requirements for ASIC design, verification, and physical implementation teams. Evaluate area ... Verilog, System Verilog, or VHDL; 3. RTL design and verification; and 4. Physical design aspects ...
ASIC Engineer 2
$143 - $222.01/hr
Define requirements for ASIC design, verification, and physical implementation teams. Evaluate area ... Verilog, System Verilog, or VHDL; 3. RTL design and verification; and 4. Physical design aspects ...
Digital ASIC Design Manager
Colorado Springs, CO · On-site
$134K/yr
We are seeking a Digital Design ASIC R&D Manager to lead and grow this capability within our ASIC ... RTL designers, and verification engineers; establish clear technical expectations and a culture of ...
Digital ASIC Design Manager
Colorado Springs, CO · On-site
$134K/yr
We are seeking a Digital Design ASIC R&D Manager to lead and grow this capability within our ASIC ... RTL designers, and verification engineers; establish clear technical expectations and a culture of ...
ASIC Engineer 2
Longmont, CO · On-site
$143 - $222.01/hr
Define requirements for ASIC design, verification, and physical implementation teams. Evaluate area ... Verilog, System Verilog, or VHDL; 3. RTL design and verification; and 4. Physical design aspects ...
ASIC Engineer 2
Longmont, CO · On-site
$143 - $222.01/hr
Define requirements for ASIC design, verification, and physical implementation teams. Evaluate area ... Verilog, System Verilog, or VHDL; 3. RTL design and verification; and 4. Physical design aspects ...
FPGA Design Eng
Boulder, CO · On-site
$129.50K - $178.40K/yr
Lockheed Martin Space is seeking a Field Programmable Gate Array (FPGA) Design Engineer to work on ... RTL design and High-Level Synthesis (HLS) methodologies within the Vitis platform. Applicants ...
FPGA Design Eng
Boulder, CO · On-site
$129.50K - $178.40K/yr
Lockheed Martin Space is seeking a Field Programmable Gate Array (FPGA) Design Engineer to work on ... RTL design and High-Level Synthesis (HLS) methodologies within the Vitis platform. Applicants ...
Telecommute Asic Rtl Design Engineer information
What are the key skills and qualifications needed to thrive as a Telecommute ASIC RTL Design Engineer, and why are they important?
What are some common challenges faced by telecommute ASIC RTL Design Engineers, and how can they be addressed?
What is a Telecommute ASIC RTL Design Engineer?
What is the difference between Telecommute Asic Rtl Design Engineer vs Telecommute Digital IC Design Engineer?
| Aspect | Telecommute Asic Rtl Design Engineer | Telecommute Digital IC Design Engineer |
|---|---|---|
| Credentials | Bachelor's or Master's in Electrical Engineering or Computer Engineering; experience with RTL coding | Bachelor's or Master's in Electrical Engineering or Computer Engineering; experience with digital circuit design |
| Work Environment | Remote, primarily designing RTL code for ASICs | Remote, focusing on digital IC architecture and design |
| Industry Usage | Common in semiconductor and electronics companies |
Both roles often require similar educational backgrounds and work remotely in the semiconductor industry. The main difference lies in their focus: RTL Design Engineers concentrate on writing RTL code for ASICs, while Digital IC Design Engineers work on broader digital circuit architecture. Candidates should choose based on their specific skills and career interests in digital design or RTL coding.
Full-time
This job post has expired today. Applications are no longer accepted.
Job description
Principal Asic Designer
At Atom Computing, we build quantum computers using arrays of optically trapped neutral atoms that will empower customers to achieve unprecedented computational breakthroughs. Join a world-class team of scientists, engineers, and business professionals to advance the state-of-the-art in quantum computing.
Atom Computing is seeking a Principal ASIC Designer to lead the development of critical technologies that power our quantum computers. In this role, you will own end-to-end design strategy—from requirements definition through silicon bring-up—while driving critical trade-off decisions across performance, power, area, and system integration constraints. You will partner closely with customers and cross-functional teams to translate evolving requirements into scalable, production-ready designs, ensuring alignment between technical execution and business objectives. As a senior technical leader, you will provide strategic guidance to executive stakeholders, shaping the long-term silicon roadmap and influencing key investment decisions. This position requires deep expertise in ASIC development and strong systems thinking. Reporting to the Hardware Engineering Manager, you'll collaborate closely with a talented group of engineers and physicists to shape the future of computing.
This position may be based in Boulder, CO, or Austin, TX.
Responsibilities
- Participate in the design and development of FPGA designs to learn the hardware architectures and designs that we intend to scale for performance and density
- Lead the research and assessment into how to best leverage ASICs to enable higher performance and higher density future generations
- Establish ASIC design processes internal to Atom Computing by defining methodologies across architecture, RTL, verification, and tapeout.
- Perform hands-on ASIC design including microarchitecture, RTL development, testing, and integration.
- Manage schedules and vendor interfaces by coordinating milestones, aligning with ASIC partners, and ensuring successful fabrication.
- Work closely with Atom Computing's quantum physicists, optical engineers, hardware and software engineers to understand use cases and deliver hardware that addresses the needs.
- Manage the product roadmap and subsystem delivery schedules for both commercial and research projects.
Experience & Education
- MS or PhD in Electrical Engineering or a related field.
- 10+ years of post-degree experience in hardware engineering, specifically in ASIC/SoC environments.
Qualifications
- Have gone through 2 or more complete ASIC design cycles.
- Experience porting designs from FPGA prototypes to ASICs
- Proficiency with RTL (SystemVerilog preferred)
- Experience in implementing large digital signal processing blocks in RTL
- Working knowledge of performance and limitations of ASIC fabs, partners, and design nodes as well as FPGA capabilities to guide selection of best fit for our applications
- Knowledge of Cadence, Synopsys, or Siemens EDA design tools
- Expertise in FPGA, microprocessor, and related digital circuit design and functions
- Mixed signal design experience is a plus.
About Atom Computing
Sourced by ZipRecruiter
Industry
It services
Company size
11 - 50 Employees
Headquarters location
Berkeley, CA, US
Year founded
2018