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Remote Asic Rtl Design Engineer Jobs in Colorado

Kiewit Corporation

Mechanical Design Engineer

Lone Tree, CO · On-site +1

$75K - $101K/yr

Design Engineering Market: Industrial Employment Type: Full Time Position Overview If you are ... Some consideration will be made for fully remote candidates that meet and exceed our requirements ...

Lochner

Airport Design Engineer

Denver, CO · On-site +1

Design of airport engineering projects including runways, taxiways, aprons, airfield lighting ... remote opportunities where business needs allow • Life insurance and disability coverage ...

Creation

Design Engineer, PCB & DFM

Denver, CO · On-site +1

The PCB Layout & Design for Manufacturing (DFM) Engineer is a highly visible technical role within ... The position offers flexibility to be remote, with a strong preference for candidates located in ...

Micron

Staff SSD Systems Design Engineer

Longmont, CO · On-site +1

$146K - $247K/yr

... and design review activities * Collaborate effectively with cross-functional engineering ... Remote and hybrid work arrangements are not supported for this position The US base salary range ...

Micron

Principal SSD Systems Design Engineer

Longmont, CO · On-site +1

$175K - $297K/yr

As a Principal SSD Systems Design Engineer within Micron's Solid State Drive (SSD) Product ... Remote and hybrid work arrangements are not supported for this position The US base salary range ...

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Remote Asic Rtl Design Engineer information

What is a remote ASIC RTL design engineer?

A Remote ASIC RTL Design Engineer is a professional who specializes in designing the Register Transfer Level (RTL) code for Application-Specific Integrated Circuits (ASICs) while working remotely. Their main responsibilities include creating and verifying digital circuit designs using hardware description languages such as Verilog or VHDL. These engineers collaborate with hardware teams to ensure functionality, performance, and power requirements are met, all while operating from a location outside of a traditional office setting. They often use remote collaboration tools and simulation software to review and validate designs before fabrication.

What are the key skills and qualifications needed to thrive as a remote ASIC RTL design engineer?

To thrive as a Remote ASIC RTL Design Engineer, you need a solid background in digital design, computer engineering, and hardware description languages like Verilog or VHDL, often supported by a relevant degree. Proficiency with industry-standard EDA tools such as Synopsys, Cadence, or Mentor Graphics, as well as experience with simulation, synthesis, and version control systems, is crucial. Strong problem-solving, self-motivation, and effective remote communication skills distinguish top performers in this role. These skills ensure accurate, efficient design cycles and effective collaboration across distributed teams, leading to successful chip delivery.

What are some common challenges faced by remote ASIC RTL design engineers, and how can they be addressed?

Remote ASIC RTL Design Engineers often face challenges such as coordinating with distributed teams across different time zones and ensuring effective communication during complex design phases. To address these issues, it’s important to establish clear documentation practices, utilize collaboration tools like version control and video conferencing, and schedule regular check-ins with team members. Additionally, staying proactive in seeking feedback and clarifying design specifications helps ensure alignment and reduces misunderstandings. Building strong virtual relationships with verification and backend teams can also streamline the handoff process and overall project flow.

What is the difference between Remote Asic Rtl Design Engineer vs Remote Digital IC Design Engineer?

AspectRemote Asic Rtl Design EngineerRemote Digital IC Design Engineer
Primary FocusRegister Transfer Level (RTL) design for ASICsDigital integrated circuit design at the IC level
Skills & CertificationsHDL (Verilog/VHDL), EDA tools, verificationHDL, circuit simulation, verification, FPGA experience
Work EnvironmentASIC design teams, hardware developmentIC design teams, semiconductor industry
Industry UsageUsed in ASIC development for various applicationsUsed in digital IC manufacturing and prototyping

Both roles involve digital design and HDL skills, but the Remote Asic Rtl Design Engineer focuses on RTL coding for ASICs, while the Remote Digital IC Design Engineer covers broader digital IC design, including FPGA and chip-level work. They share similar credentials and work environments, often overlapping in semiconductor companies.

What are the most commonly searched types of Asic Rtl Design Engineer jobs in Colorado?

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Remote Asic Rtl Design Engineer jobs near you

Senior/Principal Physical Design Engineer (remote)

Fort Collins, CO • Remote

Chelsea Search Group
See more jobs at Chelsea Search Groupexternal

$136K - $140K/yr

Full-time

Posted 5 days ago

Job description

Senior/Principal Physical Design Engineer
Job Description:
We are seeking an experienced Physical Design / P&R Engineer to take a key role in delivering complex, high-performance ASICs from RTL/netlist through GDSII and tapeout. You’ll own critical aspects of physical implementation, including floorplanning, placement, CTS, routing, timing closure, and PPA optimization, working with advanced technologies such as RISC-V, DDR, and SerDes. Using industry-leading tools including Synopsys Fusion Compiler and Siemens Calibre, you’ll solve challenging physical design problems and help drive successful silicon outcomes. This is an opportunity to make a significant technical impact while collaborating with a highly experienced, multidisciplinary ASIC engineering team.
Essential Duties and Qualifications:
• Analyze and optimize designs to meet power, performance, and area (PPA) objectives while satisfying timing, signal integrity, reliability, and manufacturability requirements.
• Collaborate closely with RTL design, verification, DFT, analog/mixed-signal, packaging, and other engineering teams to ensure successful chip integration.
• Develop and optimize floorplans incorporating complex IP and high-speed interfaces, including DDR and SerDes.
• Develop, maintain, and improve physical design flows, scripts, methodologies, and automation to increase efficiency and design quality.
• Identify and resolve congestion, routing, timing, power integrity, and physical verification issues throughout the implementation process.
• Participate in design reviews and provide recommendations regarding floorplanning, physical architecture, implementation strategy, and PPA tradeoffs.
• Perform full-chip physical design implementation from synthesized netlist through GDSII, including floorplanning, power planning, placement, clock tree synthesis (CTS), routing, optimization, and timing closure.
• Perform physical verification and signoff activities using Siemens Calibre, including DRC and LVS verification and resolution of physical design violations.
• Perform static timing analysis and drive timing closure across multiple operating modes, process corners, and design constraints.
• Provide technical guidance and mentoring to other engineers and contribute to the continued development of the team's internal physical design capabilities.
• Support final design signoff and tapeout, ensuring all applicable physical design and verification requirements have been satisfied.
• Support integration and physical implementation of third-party and internally developed IP blocks.
• Support the physical implementation and integration of RISC-V processor-based designs and subsystems, including timing, power, and physical design considerations.
• Troubleshoot complex implementation and signoff issues and drive corrective actions through resolution.
• Utilize Synopsys Fusion Compiler for physical implementation, optimization, and design closure.
Qualifications:
• 10+ years of direct industry experience with ASIC and/or SoC design.
• BSEE/MSEE or equivalent
• Excellent problem-solving skills and attention to detail.
• Experience with industry standard development tools and methodologies.
• Familiarity with RISC architectures (e.g., ARM, MIPS).
• Proficiency in Synopsys Design Compiler and other EDA tools.
• Proven track record of first-pass successes.
• Self-starter with the ability to assume leadership roles.
• Strong background in RTL based digital IC design using Verilog/SystemVerilog
• Strong understanding of digital design principles.
• Willingness to mentor and develop less experienced engineers.