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Internship Asic Rtl Design Engineer Jobs in Chicago, IL

Quanta Services

Design Engineer - Civil

Chicago, IL · On-site +1

HBK Engineering, LLC is a fully licensed, professional engineering design firm headquartered in ... Required 2.5+ years of relevant experience (not internships) * US driver's license and US work ...

Eliyan

Architecture - I/O Architect

Mundelein, IL · On-site

Mentor engineers on protocol implementation, timing constraints, and hierarchical design ... Extremely knowledgeable on RTL-to-GDSII flows, limitations, and flexibilities to improve ...

Qube Research & Technologies

FPGA Engineer

Chicago, IL · On-site

$180K - $280K/yr

We are looking for talented hardware engineers with a track record of achievement in any domain ... Develop RTL on the latest FPGAs with modern design flows * Following through into production ...

EndoSec LLC

FPGA Engineer

Elk Grove Village, IL

$128K - $164K/yr

Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded software, System ... Key Responsibilities FPGA Design and Development: Design and develop IP cores and FPGA ...

Qube Research & Technologies

FPGA Engineer

Chicago, IL · On-site

$180K - $280K/yr

We are looking for talented hardware engineers with a track record of achievement in any domain ... Develop RTL on the latest FPGAs with modern design flows * Following through into production ...

EndoSec LLC

FPGA Engineer

Elk Grove Village, IL

$128K - $164K/yr

Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded software, System ... Key Responsibilities FPGA Design and Development: Design and develop IP cores and FPGA ...

Pacer Group

Engineer 1 - ENG1

Naperville, IL · On-site

$45/hr

Responsible for applying engineering processes, design criteria, and software applications to ... None Preferred: Prior internship or co-op experience in an engineering field. Specific Skills ...

Pacer Group

Engineer 1

Naperville, IL · On-site

$45/hr

Responsible for applying engineering processes, design criteria, and software applications to ... Prior internship or co-op experience in an engineering field. * Specific Skills & Knowledge ...

Eliyan

DFT - Staff DFT Engineer

Mundelein, IL · On-site

As an Eliyan Staff DFT Engineer, you will be working at a fast-paced early-stage startup creating ... at the RTL & gate level * General knowledge of digital and AMS circuit design techniques

Motorola

Principal Antenna Engineer

Schaumburg, IL

$100K - $160K/yr

Design, simulate, and optimize custom antenna elements for wideband and multi-band applications ... Custom ASIC Development: Collaborate with our RF ASIC team on development of beamformer IC ...

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All JobsAsic Rtl Design Engineer JobsInternship Asic Rtl Design Engineer JobsInternship Asic Rtl Design Engineer Jobs in Chicago, IL

Internship Asic Rtl Design Engineer information

See Chicago, IL salary details

$96.8K

$154.7K

$208.1K

How much do internship asic rtl design engineer jobs pay per year?

As of Jun 15, 2026, the average yearly pay for internship asic rtl design engineer in Chicago, IL is $154,723.00, according to ZipRecruiter salary data. Most workers in this role earn between $135,500.00 and $185,400.00 per year, depending on experience, location, and employer.

What types of projects and responsibilities can an intern expect as an ASIC RTL Design Engineer?

As an ASIC RTL Design Engineering intern, you'll typically work on tasks such as writing and verifying RTL code using languages like Verilog or VHDL, assisting with simulation and debugging, and collaborating closely with senior engineers on real design blocks. Interns often participate in design reviews, update documentation, and may get hands-on experience with synthesis and timing analysis tools. This role is highly collaborative and provides exposure to the complete ASIC development cycle, making it an excellent opportunity to build foundational skills and gain insight into industry-standard methodologies.

What are the key skills and qualifications needed to thrive as an Internship ASIC RTL Design Engineer, and why are they important?

To thrive as an Internship ASIC RTL Design Engineer, you need a solid understanding of digital logic design, computer architecture, and proficiency in HDL languages like Verilog or VHDL, typically supported by coursework in electrical or computer engineering. Familiarity with industry-standard EDA tools such as Synopsys, Cadence, or Mentor Graphics, and simulation environments is highly valuable. Strong analytical thinking, attention to detail, and effective communication skills help interns collaborate with teams and learn quickly in a fast-paced environment. These skills and qualities are essential for contributing to complex chip design projects and ensuring accuracy and efficiency in RTL development.

What is an Internship ASIC RTL Design Engineer?

An Internship ASIC RTL (Register Transfer Level) Design Engineer is a student or recent graduate who assists in designing and developing digital integrated circuits (ICs) using hardware description languages like Verilog or VHDL. They work under the guidance of senior engineers to create, simulate, and verify RTL code for ASIC (Application Specific Integrated Circuit) projects. The role provides hands-on experience with the chip design process, including synthesis, timing analysis, and verification. Interns gain valuable exposure to industry-standard tools and methodologies, helping them prepare for a full-time engineering career.

What is the career path for ASIC design engineer?

The career path for an ASIC RTL design engineer typically starts with a bachelor's degree in electrical engineering or computer engineering, progressing to roles such as junior or senior RTL designer, then to lead or architect positions. Advancement often involves gaining experience in digital design, verification, and tools like HDL languages and EDA software, with opportunities to move into technical management or specialized roles like FPGA or system-on-chip (SoC) design.

What is RTL intern?

An RTL intern is a student or entry-level engineer gaining hands-on experience in Register Transfer Level (RTL) design, which involves developing and verifying digital hardware descriptions using hardware description languages like VHDL or Verilog. This internship typically includes tasks related to digital circuit design, simulation, and testing within an ASIC or FPGA development environment.

What is the salary of RTL design engineer?

The salary of an RTL design engineer typically ranges from $70,000 to $130,000 annually, depending on experience, location, and company size. Entry-level positions may start lower, while experienced engineers with specialized skills in hardware description languages like VHDL or Verilog can earn higher salaries.

What is the salary of ASIC design engineer?

The salary of an ASIC RTL Design Engineer typically ranges from $80,000 to $150,000 annually, depending on experience, location, and company size. Entry-level positions may start lower, while experienced engineers with specialized skills in hardware description languages and verification tools can earn higher salaries.

What is the difference between Internship Asic Rtl Design Engineer vs Asic Verification Engineer?

AspectInternship Asic Rtl Design EngineerAsic Verification Engineer
CredentialsTypically pursuing or recently completed a degree in Electrical Engineering or Computer EngineeringSimilar educational background, often with additional coursework in verification methodologies
Work EnvironmentInternship setting, supervised, focused on learning and assisting in RTL design tasksFull-time role, focused on testing and verifying RTL designs
Industry UsageUsed in semiconductor and chip design companies during early career stagesCommon in companies developing complex integrated circuits and chips

The Internship Asic Rtl Design Engineer focuses on assisting in RTL design tasks during an internship, emphasizing learning and support. In contrast, the Asic Verification Engineer is responsible for verifying RTL designs to ensure functionality. Both roles require similar educational backgrounds but differ in responsibilities and work environment, with verification roles being more advanced and permanent.

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Internship Asic Rtl Design Engineer jobs near you
Agentic AI Engineer

Agentic AI Engineer

Cadence Design Systems Inc.

Cary, IL

Full-time

Posted 12 days ago

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Agentic AI Engineer

Role Summary

Cadence is hiring early-career Agent AI Engineers to join our applied AI team building agentic systems for silicon design. You will work alongside senior AI engineers and chip-design domain experts on the core technical pillars of Cadence's agentic stack: training and adapting models for engineering tasks, engineering high-quality design context (RAG, prompt scaffolds, retrieval pipelines), and tuning the knowledge graphs and vector/graph databases that ground our agents. From day one you will be writing production code that lands in customer-facing AI products and directly accelerates how the world designs chips.

What You Will Do

  • Model Development. Train, fine-tune, distill, and evaluate LLMs / SLMs and embedding models for EDA-specific tasks. Hands-on with LoRA / PEFT, instruction tuning, preference optimization (DPO/GRPO), and rigorous eval harnesses for code and reasoning.
  • Design Context Engineering. Build the retrieval pipelines, prompt scaffolds, and tool-calling specs that feed Cadence agents the right design context (RTL, scripts, logs, reports, methodology docs) at the right token budget. Optimize for accuracy, latency, and cost.
  • Knowledge Graph & Database Tuning. Design schemas, tune ingestion, and optimize queries for graph DBs (Neo4j, ArangoDB, NebulaGraph) and vector stores (Qdrant, Weaviate, pgvector, Chroma). Keep retrieval fast, accurate, and scoped to the right design hierarchy.
  • Agent Building Blocks. Implement and harden agent tools, memory, multi-hop reasoning patterns, and guardrails. Triage production failures and iterate.
  • Data Pipelines. Curate, clean, and label datasets from EDA artifacts (RTL, waveforms, logs, reports, schematics). Build synthetic-data and self-improvement loops where appropriate.
  • Evaluation & Telemetry. Build offline benchmarks and online metrics. Help define what 'good' looks like for chip-design agents and keep regressions out of main.
  • Collaborate & Learn. Pair with senior AI engineers, BU teams, and silicon domain experts. Learn the EDA flow as you go - we'll invest in you if you invest in the craft.

Must-Have Qualifications

  • BS / MS / PhD in CS, EE, ECE, AI/ML, or a closely related field (graduating in 2025-2026; recent grads also welcome).
  • Strong fundamentals in deep learning, transformers, and modern LLM mechanics (attention, tokenization, context windows, decoding).
  • Practical hands-on experience (coursework, internships, OSS, or serious side projects) with at least TWO of: LLM fine-tuning, RAG / retrieval, agentic frameworks, knowledge graphs, vector databases.
  • Solid Python engineering: comfortable with PyTorch and Hugging Face; writes clean, tested, version-controlled code.
  • Curiosity about silicon / chip design and willingness to learn a deep technical domain on the job.
  • Strong written and verbal communication; bias to ship working code over perfect plans.

Nice-to-Have / Bonus

  • Prior internship in AI/ML at a product company or research lab with shipped artifacts.
  • Hands-on with at least one agentic framework: LangGraph, AutoGen, Cursor SDK, Claude Code, MCP-based tool-calling stacks.
  • Experience with graph DBs (Neo4j, ArangoDB, NebulaGraph) and / or vector DBs (Qdrant, Weaviate, pgvector, Chroma, Milvus).
  • ML systems / infra exposure: vLLM, TGI, Triton, distributed training, GPU performance tuning, quantization.
  • Coursework or projects in compilers, formal methods, hardware description languages (Verilog/SystemVerilog/Chisel), or EDA tools.
  • Publications, OSS contributions, or competitive ML records (Kaggle medals, MLPerf, agent benchmarks, hackathon wins).
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