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Temporary Asic Rtl Design Engineer Jobs in Chicago, IL

Eliyan

PD - Principal, Physical Design

Mundelein, IL

As an Eliyan Principal Physical Design Engineer, you will be working at a fast-paced early-stage ... You will drive the development of cutting-edge ASICs from RTL to GDSII. You will work with a cross ...

Actalent

Electrical Design Engineer

Naperville, IL

$40 - $60/hr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

Electrical Design Engineer The Electrical Design Engineer supports the testing, development, and ... If eligible, the benefits available for this temporary role may include the following: * Medical ...

New

Actalent

FPGA Design Engineer

Schaumburg, IL

$55 - $80/hr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

FPGA Design Engineer We are seeking a skilled FPGA Design Engineer to join a leading defense ... If eligible, the benefits available for this temporary role may include the following: * Medical ...

Actalent

Fpga Design Engineer

Chicago, IL

$55 - $80/hr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

FPGA Design Engineer We are seeking a skilled FPGA Design Engineer to join a leading defense ... If eligible, the benefits available for this temporary role may include the following: * Medical ...

Edgehog Trading

Junior FPGA Developer

Chicago, IL · On-site

$100 - $175/hr

  • Medical

  • Dental

  • Vision

  • Retirement

  • PTO

Our team spans trading, engineering, and business operations, working together to build and support ... Design, implement, and verify RTL logic in Verilog or SystemVerilog targeting ultra-low-latency ...

Edgehog Trading

Junior FPGA Developer

Chicago, IL · On-site

  • Medical

  • Dental

  • Vision

  • Retirement

  • PTO

Our team spans trading, engineering, and business operations, working together to build and support ... Design, implement, and verify RTL logic in Verilog or SystemVerilog targeting ultra-low-latency ...

Actalent

Electrical Design Engineer - Automation

Naperville, IL

$40 - $60/hr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

Electrical Design Engineer The Electrical Design Engineer supports the testing, development, and ... If eligible, the benefits available for this temporary role may include the following: * Medical ...

New

Jump Trading

Campus FPGA Engineer (Intern)

Chicago, IL · On-site

$250K/yr

Experience with FPGA or other hardware/systems design and development * Experience with RTL (SystemVerilog/Verilog/VHDL) * Previous internship experience in hardware or low-level software engineering

Jump Trading

Campus FPGA Engineer (Intern)

Chicago, IL · On-site

$250K/yr

Experience with FPGA or other hardware/systems design and development * Experience with RTL (SystemVerilog/Verilog/VHDL) * Previous internship experience in hardware or low-level software engineering

Jump Trading

Campus FPGA Engineer (Intern)

Chicago, IL · On-site

$250K/yr

Experience with FPGA or other hardware/systems design and development * Experience with RTL (SystemVerilog/Verilog/VHDL) * Previous internship experience in hardware or low-level software engineering

Ventura Solutions LLC

Design Verification Engineer

Chicago, IL · On-site

$45 - $55/hr

  • Medical

  • Dental

  • Retirement

  • PTO

Our client is seeking an experienced Design Verification Engineer to lead the planning, development ... On the staffing side, we help source, screen, and on-board reputable employees to fill temporary ...

Ventura Solutions LLC

Design Verification Engineer

Chicago, IL

$45 - $55/hr

  • Medical

  • Dental

  • Retirement

  • PTO

Our client is seeking an experienced Design Verification Engineer to lead the planning, development ... On the staffing side, we help source, screen, and on-board reputable employees to fill temporary ...

Ventura Solutions LLC

Design Verification Engineer

Chicago, IL · On-site

$45 - $55/hr

  • Medical

  • Dental

  • Retirement

  • PTO

Our client is seeking an experienced Design Verification Engineer to lead the planning, development ... On the staffing side, we help source, screen, and on-board reputable employees to fill temporary ...

MatrixSpace

FPGA Engineer

Hoffman Estates, IL · Remote

$150K - $200K/yr

Design and develop FPGA architectures and high-throughput data paths for radar sensing systems ... Strong RTL development skills using System Verilog, Verilog, VHDL, HLS, or similar, from ...

EndoSec LLC

FPGA Engineer

Elk Grove Village, IL

$128K - $164K/yr

Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded software, System ... Key Responsibilities FPGA Design and Development: Design and develop IP cores and FPGA ...

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Showing results 21-40

All JobsAsic Rtl Design Engineer JobsTemporary Asic Rtl Design Engineer JobsTemporary Asic Rtl Design Engineer Jobs in Chicago, IL

Temporary Asic Rtl Design Engineer information

See Chicago, IL salary details

$96.8K

$154.7K

$208.1K

How much do temporary asic rtl design engineer jobs pay per year?

As of Aug 19, 2026, the average yearly pay for temporary asic rtl design engineer in Chicago, IL is $154,723.00, according to ZipRecruiter salary data. Most workers in this role earn between $135,500.00 and $185,400.00 per year, depending on experience, location, and employer.

What is the difference between Temporary Asic Rtl Design Engineer vs Temporary FPGA Design Engineer?

AspectTemporary Asic Rtl Design EngineerTemporary FPGA Design Engineer
Primary FocusDesigning RTL code for ASIC chipsDesigning FPGA logic and configurations
Skills & CertificationsVerilog/VHDL, ASIC design flow, simulation toolsVerilog/VHDL, FPGA development tools, synthesis
Work EnvironmentSemiconductor companies, ASIC design teamsFPGA development labs, prototyping environments
Industry UsageUsed in high-volume chip manufacturingUsed for prototyping, testing, and low-volume products

Both roles involve RTL design using Verilog or VHDL, but the Temporary Asic Rtl Design Engineer focuses on ASIC chip development, while the Temporary FPGA Design Engineer specializes in FPGA-based prototyping and testing. The choice depends on whether the project aims for mass production or flexible, rapid development.

What are the most commonly searched types of Asic Rtl Design Engineer jobs in Chicago, IL?

The most popular types of Asic Rtl Design Engineer jobs in Chicago, IL are:

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For Temporary Asic Rtl Design Engineer jobs in Chicago, IL, the most frequently searched job titles are:

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The top searched job categories for Temporary Asic Rtl Design Engineer jobs in Chicago, IL are:

Temporary Asic Rtl Design Engineer jobs near you

PD - Principal, Physical Design

Eliyan

Mundelein, IL

Full-time

Re-posted 11 days ago

Job description

Join the leading chiplet startup! As an Eliyan Principal Physical Design Engineer, you will be working at a fast-paced early-stage startup creating technologies that fuel tomorrow’s chiplet based systems with best-in-class power, area, manufacturability, and design flexibility. You will drive the development of cutting-edge ASICs from RTL to GDSII.  You will work with a cross-functional team of industry experts that operate from first principles, innovate, and push the envelope to create high-volume and high-performance manufacturable products. In this role, you will oversee and optimize the entire design flow, including synthesis, place-and-route (PnR), static timing analysis (STA), electromigration/IR drop analysis (EM/IR), and physical verification (PV). You will also focus on developing and improving design flows and methodologies to ensure high-quality, on-time delivery. We offer a fun work environment with excellent benefits.
Responsibilities:
  • Architecture and packaging driven floorplanning and integration so physical partitions match system and package constraints
  • Well defined boundaries with lego style pin alignment and consistent interface placement across chip and blocks
  • Feedthrough, repeater and bus planning with early reservation of routing corridors, layers, and resources for cross block connectivity.
  • Define clocking architecture methodology selecting spine and rib, H tree, or mesh to optimize power, skew, latency, and robustness.
  • Establish CTS methodology including skew and latency targets, buffer and ICG strategy, NDR and shielding rules for critical clock routes.
  • Define skew groups and balancing strategy across library corners, ensuring consistent behavior under MMMC variations and derates.
  • Drive clock constraint quality across hierarchy with clean chip to block and block to chip handoff for signoff readiness.
  • Define DRC aware power grid architecture including rings, straps, and mesh, matching metal resistivity assumptions to IR drop targets and EM limits.
  • Ensure careful planning around analog routing with keepouts, shielding, spacing, and grid topology choices that preserve sensitive nets and meet DRC.
  • Drive lego aligned power mesh alignment across top level, subsystem, and block level with consistent strap pitch, via patterns, and clean connectivity.
  • Lead early and signoff EM and IR analysis, identify hotspots, and implement grid reinforcement and via optimization without routing or congestion penalties.
  • Align power planning with floorplan and package constraints including bump map, current demand, and entry points to minimize noise and IR drop.
Qualifications:
  • 8 to 12 years ASIC physical design experience owning floorplanning integration clocking and power planning from early feasibility through signoff and tapeout on complex SoCs
  • Expert in architecture and package driven hierarchy planning with lego aligned boundaries pin strategy feedthrough repeater bus planning plus CTS methodologies including spine rib H tree or mesh
  • Strong EM IR PV and STA awareness with MMMC and library corner skew group balancing advanced node exposure TSMC 3nm 2nm or Samsung 2nm and functional ECO execution experience

We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses and identifying potential inconsistencies or verification signals in application materials based on available information. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.