1

Dft Jobs in Illinois (NOW HIRING)

Design Engineer I

Cary, IL · On-site

$88K - $165K/yr

As such we are seeking an experienced DFT engineer which role will span across the full spectrum of the DFT implementation: from architecture definition through silicon testing and debug. A bonus ...

Site-specific tasks may include bonded freight handling, DFT compliance, and weekly bond checks. Qualifications: Required: Age 18+, able to lift up to 50 lbs, strong physical stamina. Preferred: High ...

Site-specific tasks may include bonded freight handling, DFT compliance, and weekly bond checks. Qualifications: Required: * Age 18+ * Able to lift up to 50 lbs * Strong physical stamina Preferred:

Test Engineer

Rockford, IL · On-site

$65K - $95K/yr

Experience supporting design for manufacturability and testability (DFM/DFT) initiatives. * Ability to manage small engineering projects, vendors, and equipment build schedules. Salary Description ...

Test Engineer

Rockford, IL · On-site

$65K - $95K/yr

Experience supporting design for manufacturability and testability (DFM/DFT) initiatives. * Ability to manage small engineering projects, vendors, and equipment build schedules.

Design for Testability (DFT) Required Qualifications * Bachelor's degree in Electrical Engineering. * 5+ years of hands-on power electronics hardware development experience. * Experience with: * High ...

Test Engineer

Rockford, IL · On-site

$65K - $95K/yr

Experience supporting design for manufacturability and testability (DFM/DFT) initiatives. * Ability to manage small engineering projects, vendors, and equipment build schedules.

next page

Showing results 1-20

Dft information

See Illinois salary details

$67.3K

$75.7K

$82.4K

How much do dft jobs pay per year?

As of Sep 5, 2026, the average yearly pay for dft in Illinois is $75,680.00, according to ZipRecruiter salary data. Most workers in this role earn between $71,700.00 and $79,500.00 per year, depending on experience, location, and employer.

What is a DFT engineer?

DFT engineers, or Design for Test engineers, are professionals in the semiconductor industry who specialize in designing and implementing testability features in integrated circuits (ICs) and systems-on-chip (SoCs). Their primary role is to ensure that chips can be efficiently and effectively tested for manufacturing defects after fabrication. This involves adding test structures, developing test methodologies, and working closely with design and verification teams to optimize test coverage and reduce the cost of testing. DFT engineers play a critical role in improving product quality and yield in chip manufacturing.

What are the key skills and qualifications needed to thrive as a Design for Test (DFT) engineer?

To thrive as a Design for Test (DFT) Engineer, you need a solid background in digital design, VLSI concepts, and experience with ASIC/FPGA design, typically supported by a degree in electrical or computer engineering. Proficiency with EDA tools such as Synopsys DFT Compiler, Mentor Tessent, and scripting languages like TCL or Python is essential, along with knowledge of test methodologies like scan insertion and ATPG. Strong problem-solving abilities, attention to detail, and effective communication skills help in debugging complex issues and collaborating across teams. These skills are vital for ensuring high-quality, testable hardware designs that meet production and reliability standards.

What are some common challenges faced by DFT engineers when collaborating with design and verification teams?

DFT engineers often encounter challenges ensuring their test structures integrate seamlessly with the main design and verification flows. Balancing test coverage with minimal impact on design performance requires ongoing communication and compromise. Additionally, DFT engineers must frequently align on methodologies and resolve conflicts between testability requirements and design constraints, making cross-functional teamwork essential for success.

What is the difference between Dft vs Draftsman?

AspectDftDraftsman
Required CredentialsTypically requires a diploma or certification in drafting or engineeringOften requires a diploma or technical training in drafting or architecture
Work EnvironmentWorks in engineering, construction, or manufacturing settingsWorks mainly in architectural or engineering offices
Industry UsageCommonly used in engineering, manufacturing, and construction industriesPrimarily used in architecture and civil engineering sectors
Job FocusDesigning and creating technical drawings for engineering projectsPreparing detailed architectural or structural drawings

In summary, Dft and Draftsman roles share similar skills and work environments, often requiring technical diplomas. Dft typically refers to a broader engineering drafting role, while Draftsman is more focused on architectural drawings. Both are essential in their respective industries for translating concepts into technical plans.

Is DFT a good career?

A DFT (Design for Test) engineer specializes in developing testing methods for electronic circuits and systems, often requiring knowledge of digital and analog testing techniques, CAD tools, and industry standards. It can be a stable career with opportunities in electronics manufacturing, semiconductor, and technology companies, especially for those with strong technical skills and certifications. The role typically involves problem-solving, attention to detail, and staying current with testing technologies.

Is DFT a good place to work?

DFT, as a job title, typically refers to a role such as a Design for Test engineer or a similar technical position. The work environment and job satisfaction depend on the company, industry, and specific role, but these positions often require technical skills and attention to detail. Overall, the suitability of DFT as a workplace varies based on individual preferences and organizational culture.

What are the most commonly searched types of Dft jobs in Illinois?

The most popular types of Dft jobs in Illinois are:

Infographic showing various Dft job openings in Illinois as of August 2026, with employment types broken down into 100% Full Time. Highlights an 100% In-person job distribution, with an average salary of $75,680 per year, or $36.4 per hour.

$88K - $165K/yr

Full-time

Medical, Dental, Vision, Retirement, PTO

Posted 10 days ago


Cadence Design Systems rating

9.0

Company rating: 9.0 out of 10

Based on 5 frontline employees who took The Breakroom Quiz

33rd of 247 rated software companies


Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

We are a small group of individuals designing among the most complex chip in the world getting into the award-winning Cadence Design Systems Palladium platform...

As such we are seeking an experienced DFT engineer which role will span across the full spectrum of the DFT implementation: from architecture definition through silicon testing and debug.

A bonus, this individual will have cross functional teams' interactions not only within our group; but across Cadence and the multiple BU involved in our developments.

Key responsibilities:

  • Define and implement SoC level DFT architecture for large and complex designs.
  • Develop, integrate, and support SCAN, ATPG, MBIST, BSCAN and iJTAG.
  • Perform DFT insertion, verification, and coverage analysis at block and SoC levels.
  • Drive pre-silicon DFT sign-off, including DRC closure and coverage targets.
  • Support post-silicon debug, failure analysis and yield learning.
  • Collaborate with RTL, verification, physical design and operation teams.

Qualifications:

  • BS degree
  • At least 3 years of hands-on experience in SoC DFT.

Must-have skills:

  • Strong expertise in SCAN, ATPG, MBIST.
  • Experience with pre-silicon validation and post-silicon debug.
  • Strong problem solving and debugging skills.
  • Ability to work effectively in a cross-functional engineering environment.

Good-to-have skills:

  • Scripting experience (TCL, Perl, Python or equivalent) for flow automation and analysis.
  • Experience with IP-level DFT integration and reuse.
  • Exposure to low-power DFT considerations and complex clocking architectures.
  • Familiarity with manufacturing test flows and silicon yield improvement.

The annual salary range for California is $88,900 to $165,100. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We're doing work that matters. Help us solve what others can't.

What Cadence Design Systems employees say

Workplace

Get the full story on Breakroom