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Cpu Rtl Design Engineer Jobs in Illinois (NOW HIRING)

Eliyan

Digital - SerDes Digital Design Lead

Mundelein, IL

$138K/yr

... Engineering, or related fields * 12+ years of experience in digital design of high-speed SerDes, PHY, or transceiver IPs with proven tapeout experience at 112G PAM4 or higher data rates * Strong RTL ...

IMC

Hardware Engineer

Chicago, IL · On-site

$127K - $168K/yr

IMC is seeking a Hardware Engineer to join our Global Hardware team and help develop the next ... Design and implement RTL for next-generation ASIC platforms using SystemVerilog * Contribute to ...

IMC

Hardware Engineer

Chicago, IL · On-site

$127K - $167K/yr

IMC is seeking a Hardware Engineer to join our Global Hardware team and help develop the next ... Design and implement RTL for next-generation ASIC platforms using SystemVerilog * Contribute to ...

IMC

Hardware Engineer

Chicago, IL · On-site

$127K - $167K/yr

IMC is seeking a Hardware Engineer to join our Global Hardware team and help develop the next ... Design and implement RTL for next-generation ASIC platforms using SystemVerilog * Contribute to ...

Socket.dev

Hardware Engineer

Chicago, IL · On-site

$200 - $225/hr

IMC is seeking a Hardware Engineer to join our Global Hardware team and help develop the next ... Design and implement RTL for next-generation ASIC platforms using SystemVerilog * Contribute to ...

Jump Trading

Campus FPGA Engineer (Intern)

Chicago, IL · On-site

$250K/yr

Experience with FPGA or other hardware/systems design and development * Experience with RTL ... Any programming close to the metal with CPU, GPU, microprocessors, etc. * Linux kernel and driver ...

Jump Trading

Campus FPGA Engineer (Intern)

Chicago, IL · On-site

$250K/yr

Experience with FPGA or other hardware/systems design and development * Experience with RTL ... Any programming close to the metal with CPU, GPU, microprocessors, etc. * Linux kernel and driver ...

Edgehog Trading

Junior FPGA Developer

Chicago, IL · On-site

Our team spans trading, engineering, and business operations, working together to build and support ... Design, implement, and verify RTL logic in Verilog or SystemVerilog targeting ultra-low-latency ...

Rivian

Sr. Engineer, Equipment Design

Normal, IL · On-site

$98K - $123K/yr

Analyzes and reviews CPU/OEE and looks for improvement opportunities in equipment design using ... Coaches and mentors engineering team regarding the design of lean material handling equipment

Eliyan

PD - Principal, Physical Design

Mundelein, IL

As an Eliyan Principal Physical Design Engineer, you will be working at a fast-paced early-stage ... You will drive the development of cutting-edge ASICs from RTL to GDSII. You will work with a cross ...

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All JobsCpu Rtl Design Engineer JobsCpu Rtl Design Engineer Jobs in Illinois

Cpu Rtl Design Engineer information

See Illinois salary details

$39.2K

$85.4K

$153.6K

How much do cpu rtl design engineer jobs pay per year?

As of Aug 11, 2026, the average yearly pay for cpu rtl design engineer in Illinois is $85,419.00, according to ZipRecruiter salary data. Most workers in this role earn between $65,900.00 and $95,400.00 per year, depending on experience, location, and employer.

What is the difference between Cpu Rtl Design Engineer vs Cpu Verification Engineer?

AspectCpu Rtl Design EngineerCpu Verification Engineer
Primary FocusDesigning and developing RTL code for CPU componentsVerifying and testing RTL designs for correctness
Skills & CertificationsHDL languages (Verilog/VHDL), FPGA/ASIC design experienceHDL, testbench development, simulation tools
Work EnvironmentDesign teams, hardware development labsVerification teams, simulation environments
Industry UsageSemiconductor companies, CPU design firmsASIC/FPGA verification, chip validation

While both roles require HDL knowledge and work within hardware design environments, Cpu Rtl Design Engineers focus on creating the RTL code for CPU components, whereas Cpu Verification Engineers concentrate on testing and validating those designs to ensure functionality and performance.

What are some common challenges faced by CPU RTL design engineers when collaborating with verification and architecture teams?

CPU RTL Design Engineers often work closely with both verification and architecture teams to ensure that the design meets functional and performance requirements. A common challenge is ensuring clear communication of design intent and handling feedback from verification regarding corner cases or bugs. Balancing architectural changes with design timelines and maintaining synchronization across multiple teams can be demanding. Successful engineers proactively document their work, participate in regular sync-ups, and are open to iterative improvements based on collaborative feedback.

What are the key skills and qualifications needed to thrive as a CPU RTL design engineer?

To thrive as a CPU RTL Design Engineer, you need a strong background in digital logic design, computer architecture, and proficiency in hardware description languages like Verilog or VHDL, typically supported by a degree in electrical or computer engineering. Familiarity with industry-standard EDA tools such as Synopsys or Cadence, and experience with simulation, synthesis, and verification methodologies are essential. Strong problem-solving skills, attention to detail, and effective teamwork are crucial soft skills for success in this role. These competencies enable the accurate implementation, debugging, and optimization of complex CPU designs, ensuring performance and reliability in final hardware products.

What is a CPU RTL design engineer?

CPU RTL (Register Transfer Level) Design Engineers are specialized hardware engineers who design, implement, and verify the digital logic that forms the core of computer processors. They use hardware description languages like Verilog or VHDL to create and simulate the functional blocks of CPUs, ensuring correct operation and optimal performance. Their work involves close collaboration with architecture, verification, and physical design teams to bring processor designs from conception to silicon. They also debug and optimize designs to meet power, speed, and area goals.
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What job categories do people searching Cpu Rtl Design Engineer jobs in Illinois look for? The top searched job categories for Cpu Rtl Design Engineer jobs in Illinois are:
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Cpu Rtl Design Engineer jobs near you
Infographic showing various Cpu Rtl Design Engineer job openings in Illinois as of August 2026, with employment types broken down into 1% Internship, 87% Full Time, 8% Part Time, and 4% Contract. Highlights an 84% Physical, 5% Hybrid, and 11% Remote job distribution, with an average salary of $85,419 per year, or $41.1 per hour.

Digital - SerDes Digital Design Lead

Eliyan

Mundelein, IL

$138K/yr

Full-time

Re-posted 21 days ago

Job description

Join the leading chiplet startup!  As the SerDes Digital Design Lead at Eliyan, you will drive the architecture and implementation of next-generation high-speed serial link IPs targeting 224G and 448G data rates for chiplet-based systems with best-in-class power, area, manufacturability, and design flexibility.  You will lead the digital design of SerDes transmitter and receiver datapaths, clock and data recovery (CDR) digital logic, equalization engines, and PHY-level controller logic for cutting-edge interconnect products.  You will work with a cross-functional team of experts that operate from first principles, innovate and push the envelope to create high-volume and high-performance manufacturable products.  We offer a fun work environment with excellent benefits.
Key Responsibilities:
  • Lead the micro-architecture definition and RTL implementation of high-speed SerDes digital blocks targeting 224G PAM4 and 448G signaling, including DSP-based equalization (FFE, DFE, CTLE digital controls), CDR loop logic, and adaptation engines
  • Design and optimize PHY-level digital logic including TX driver control, RX datapath, PCS sublayers, lane alignment, deskew, and gear-boxing/rate-matching logic
  • Architect and implement forward error correction (FEC) encoder/decoder blocks including RS-FEC (KP4/KP8), interleaving, and low-latency FEC architectures optimized for 224G/448G link budgets
  • Drive RTL design quality through lint, CDC/RDC analysis, synthesis optimization, and close collaboration with physical design and timing closure teams on advanced FinFET/GAA process nodes
  • Collaborate closely with analog/mixed-signal designers on SerDes AFE integration, digital-to-analog interface specification, calibration sequencing, and AMS co-simulation bring-up
  • Own design deliverables and milestones from RTL development through tapeout signoff; coordinate with verification, DFT, and backend teams to meet aggressive schedules
  • Define and implement auto-negotiation, link training, and PHY initialization state machines compliant with IEEE 802.3
  • Develop power-efficient digital architectures with emphasis on clock gating, voltage scaling, and low-power design techniques for data center and AI/ML interconnect applications
  • Participate in standards bodies and stay current with emerging 224G/448G specifications, OIF CEI, and next-generation interconnect standards
  • Design firmware-accessible register interfaces, configuration/calibration logic, and DPI-based firmware co-simulation hooks for PHY bring-up and debug
  • Support post-silicon characterization and debug activities; correlate silicon measurements with pre-silicon simulation results to drive design improvements
Qualifications:
  • Masters or Ph.D in Electrical Engineering, Computer Engineering, or related fields
  • 12+ years of experience in digital design of high-speed SerDes, PHY, or transceiver IPs with proven tapeout experience at 112G PAM4 or higher data rates
  • Strong RTL design skills in SystemVerilog with deep understanding of synthesis, timing closure, CDC/RDC, and design-for-test (DFT) methodologies
  • Expert-level knowledge of SerDes DSP architectures including FFE, DFE, MLSE, CTLE digital controls, CDR loop dynamics, and adaptation/calibration algorithms for PAM4 signaling
  • Strong working knowledge of IEEE 802.3 (100G/200G/400G/800G/1.6T), OIF CEI specifications, FEC architectures (RS-FEC KP4/KP8), and/or die-to-die standards such as UCIe
  • Hands-on experience with high-speed digital design on advanced process nodes (5nm, 3nm, or below) with understanding of FinFET/GAA device implications on circuit performance and power
  • Experience working at the digital-analog boundary including specification of DAC/ADC interfaces, calibration state machines, and integration with mixed-signal simulation environments
  • Demonstrated technical leadership with ability to mentor engineers, drive architectural decisions, and deliver silicon on aggressive schedules in startup or high-growth environments
  • Experience with optical/electrical interconnects (VCSEL, EML), chiplet D2D interfaces, DRAM PHYs, or HBM memory interfaces a plus

We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses and identifying potential inconsistencies or verification signals in application materials based on available information. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.