Scope & Responsibilities Our client, a leading global technology and engineering services ... Define engagement models and delivery architectures spanning RTL design, DFT, physical design ...
Scope & Responsibilities Our client, a leading global technology and engineering services ... Define engagement models and delivery architectures spanning RTL design, DFT, physical design ...
Lead Design Engineer
Cary, IL ยท On-site
$104K - $136K/yr
Interface with Front End RTL design teams and Back End Verification teams Position Requirements/Qualifications:
Lead Design Engineer
Cary, IL ยท On-site
$104K - $136K/yr
Interface with Front End RTL design teams and Back End Verification teams Position Requirements/Qualifications:
Design Engineer I
$88K - $165K/yr
As such we are seeking an experienced DFT engineer which role will span across the full spectrum of ... Collaborate with RTL, verification, physical design and operation teams. Qualifications: * BS ...
Design Engineer I
$88K - $165K/yr
As such we are seeking an experienced DFT engineer which role will span across the full spectrum of ... Collaborate with RTL, verification, physical design and operation teams. Qualifications: * BS ...
Hardware Engineer
Chicago, IL ยท On-site
$127K - $167K/yr
IMC is seeking a Hardware Engineer to join our Global Hardware team and help develop the next ... Design and implement RTL for next-generation ASIC platforms using SystemVerilog * Contribute to ...
Hardware Engineer
Chicago, IL ยท On-site
$127K - $167K/yr
IMC is seeking a Hardware Engineer to join our Global Hardware team and help develop the next ... Design and implement RTL for next-generation ASIC platforms using SystemVerilog * Contribute to ...
Principal Design Engineer
Cary, IL ยท On-site
$136K - $253K/yr
Interface with Front End RTL design teams and Back End Verification teams Position Requirements/Qualifications:
Principal Design Engineer
Cary, IL ยท On-site
$136K - $253K/yr
Interface with Front End RTL design teams and Back End Verification teams Position Requirements/Qualifications:
Design Verification Engineer
Chicago, IL ยท On-site
$140K - $171K/yr
Design Verification Engineer We are seeking a detail-oriented Design Verification Engineer to ... In this role, you will act as the vital link between our RTL design teams, system architects, and ...
Design Verification Engineer
Chicago, IL ยท On-site
$140K - $171K/yr
Design Verification Engineer We are seeking a detail-oriented Design Verification Engineer to ... In this role, you will act as the vital link between our RTL design teams, system architects, and ...
Hardware Engineer
Chicago, IL ยท On-site
$127K - $168K/yr
IMC is seeking a Hardware Engineer to join our Global Hardware team and help develop the next ... Design and implement RTL for next-generation ASIC platforms using SystemVerilog * Contribute to ...
Hardware Engineer
Chicago, IL ยท On-site
$127K - $168K/yr
IMC is seeking a Hardware Engineer to join our Global Hardware team and help develop the next ... Design and implement RTL for next-generation ASIC platforms using SystemVerilog * Contribute to ...
Hardware Engineer
Chicago, IL ยท On-site
$127K - $167K/yr
IMC is seeking a Hardware Engineer to join our Global Hardware team and help develop the next ... Design and implement RTL for next-generation ASIC platforms using SystemVerilog * Contribute to ...
Hardware Engineer
Chicago, IL ยท On-site
$127K - $167K/yr
IMC is seeking a Hardware Engineer to join our Global Hardware team and help develop the next ... Design and implement RTL for next-generation ASIC platforms using SystemVerilog * Contribute to ...
Campus FPGA Engineer (Intern)
Chicago, IL ยท On-site
$250K/yr
Experience with FPGA or other hardware/systems design and development * Experience with RTL ... Any programming close to the metal with CPU, GPU, microprocessors, etc. * Linux kernel and driver ...
Campus FPGA Engineer (Intern)
Chicago, IL ยท On-site
$250K/yr
Experience with FPGA or other hardware/systems design and development * Experience with RTL ... Any programming close to the metal with CPU, GPU, microprocessors, etc. * Linux kernel and driver ...
Experience with FPGA or other hardware/systems design and development * Experience with RTL ... Any programming close to the metal with CPU, GPU, microprocessors, etc. * Linux kernel and driver ...
Experience with FPGA or other hardware/systems design and development * Experience with RTL ... Any programming close to the metal with CPU, GPU, microprocessors, etc. * Linux kernel and driver ...
Campus FPGA Engineer (Intern)
Chicago, IL ยท On-site
$250K/yr
Experience with FPGA or other hardware/systems design and development * Experience with RTL ... Any programming close to the metal with CPU, GPU, microprocessors, etc. * Linux kernel and driver ...
Campus FPGA Engineer (Intern)
Chicago, IL ยท On-site
$250K/yr
Experience with FPGA or other hardware/systems design and development * Experience with RTL ... Any programming close to the metal with CPU, GPU, microprocessors, etc. * Linux kernel and driver ...
Campus FPGA Engineer (Intern)
Chicago, IL ยท On-site
$250K/yr
Experience with FPGA or other hardware/systems design and development * Experience with RTL ... Any programming close to the metal with CPU, GPU, microprocessors, etc. * Linux kernel and driver ...
Campus FPGA Engineer (Intern)
Chicago, IL ยท On-site
$250K/yr
Experience with FPGA or other hardware/systems design and development * Experience with RTL ... Any programming close to the metal with CPU, GPU, microprocessors, etc. * Linux kernel and driver ...
... RTL design and verification through synthesis, place-and-route, timing, power, signoff, and ... Define and report KPIs - cycle-time reduction, engineer-hours saved, iteration count, first-pass ...
... RTL design and verification through synthesis, place-and-route, timing, power, signoff, and ... Define and report KPIs - cycle-time reduction, engineer-hours saved, iteration count, first-pass ...
As an FPGA Design Engineer, you will join our diverse team and be responsible for research ... as RTL/gate level simulation, synthesis, place and route, static timing analysis, and power ...
New
As an FPGA Design Engineer, you will join our diverse team and be responsible for research ... as RTL/gate level simulation, synthesis, place and route, static timing analysis, and power ...
New
As an FPGA Design Engineer, you will join our diverse team and be responsible for research ... Proficient in FPGA design flow including items such as RTL/gate level simulation, synthesis, place ...
As an FPGA Design Engineer, you will join our diverse team and be responsible for research ... Proficient in FPGA design flow including items such as RTL/gate level simulation, synthesis, place ...
As an FPGA Design Engineer, you will join our diverse team and be responsible for research ... Proficient in FPGA design flow including items such as RTL/gate level simulation, synthesis, place ...
As an FPGA Design Engineer, you will join our diverse team and be responsible for research ... Proficient in FPGA design flow including items such as RTL/gate level simulation, synthesis, place ...
Junior FPGA Developer
Chicago, IL ยท On-site
Our team spans trading, engineering, and business operations, working together to build and support ... Design, implement, and verify RTL logic in Verilog or SystemVerilog targeting ultra-low-latency ...
Junior FPGA Developer
Chicago, IL ยท On-site
Our team spans trading, engineering, and business operations, working together to build and support ... Design, implement, and verify RTL logic in Verilog or SystemVerilog targeting ultra-low-latency ...
We are seeking a motivated FPGA Design Engineering intern to join our Hardware-in-the-Loop (HIL ... RTL Development: Write robust custom RTL modules in SystemVerilog, Verilog, or VHDL to manage high ...
We are seeking a motivated FPGA Design Engineering intern to join our Hardware-in-the-Loop (HIL ... RTL Development: Write robust custom RTL modules in SystemVerilog, Verilog, or VHDL to manage high ...
We are seeking a motivated FPGA Design Engineering intern to join our Hardware-in-the-Loop (HIL ... RTL Development: Write robust custom RTL modules in SystemVerilog, Verilog, or VHDL to manage high ...
We are seeking a motivated FPGA Design Engineering intern to join our Hardware-in-the-Loop (HIL ... RTL Development: Write robust custom RTL modules in SystemVerilog, Verilog, or VHDL to manage high ...
UIUC Research Park Intern - FPGA Design
Champaign, IL ยท On-site
$25 - $40/hr
We are seeking a motivated FPGA Design Engineering intern to join our Hardware-in-the-Loop (HIL ... RTL Development: Write robust custom RTL modules in SystemVerilog, Verilog, or VHDL to manage high ...
UIUC Research Park Intern - FPGA Design
Champaign, IL ยท On-site
$25 - $40/hr
We are seeking a motivated FPGA Design Engineering intern to join our Hardware-in-the-Loop (HIL ... RTL Development: Write robust custom RTL modules in SystemVerilog, Verilog, or VHDL to manage high ...
Cpu Rtl Design Engineer information
See Illinois salary details
$39.2K - $49.6K
2% of jobs
$49.6K - $60K
11% of jobs
$65.6K is the 25th percentile. Wages below this are outliers.
$60K - $70.4K
23% of jobs
The median wage is $77.1K / yr.
$70.4K - $80.8K
22% of jobs
$80.8K - $91.2K
17% of jobs
$91.5K is the 75th percentile. Wages above this are outliers.
$91.2K - $101.6K
9% of jobs
$101.6K - $112K
6% of jobs
$112K - $122.4K
3% of jobs
$122.4K - $132.8K
3% of jobs
$132.8K - $143.2K
2% of jobs
$143.2K - $153.6K
1% of jobs
$39.2K
$85.4K
$153.6K
How much do cpu rtl design engineer jobs pay per year?
What is a CPU RTL design engineer?
What are the key skills and qualifications needed to thrive as a CPU RTL design engineer?
What are some common challenges faced by CPU RTL design engineers when collaborating with verification and architecture teams?
What is the difference between Cpu Rtl Design Engineer vs Cpu Verification Engineer?
| Aspect | Cpu Rtl Design Engineer | Cpu Verification Engineer |
|---|---|---|
| Primary Focus | Designing and developing RTL code for CPU components | Verifying and testing RTL designs for correctness |
| Skills & Certifications | HDL languages (Verilog/VHDL), FPGA/ASIC design experience | HDL, testbench development, simulation tools |
| Work Environment | Design teams, hardware development labs | Verification teams, simulation environments |
| Industry Usage | Semiconductor companies, CPU design firms | ASIC/FPGA verification, chip validation |
While both roles require HDL knowledge and work within hardware design environments, Cpu Rtl Design Engineers focus on creating the RTL code for CPU components, whereas Cpu Verification Engineers concentrate on testing and validating those designs to ensure functionality and performance.
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Job description
Scope & Responsibilities
Our client, a leading global technology and engineering services organization, is seeking a senior technical leader to define and shape solution strategy across complex SoC and ASIC design engagements.
This is a senior individual contributor role serving as a primary technical authority in pre-sales and solutioning environments. The leader will partner directly with semiconductor clients to shape pursuit strategy, lead technical discovery, architect solutions, and ensure proposals are grounded in credible engineering and delivery frameworks. This role does not carry a sales quota.
Key Responsibilities
- Lead technical solutioning for ASIC and SoC design pursuits, from initial discovery and scoping through proposal development and client presentations.
- Define engagement models and delivery architectures spanning RTL design, DFT, physical design, signoff, verification, and tape-out support.
- Develop differentiated technical solutions across synthesis, place-and-route, functional verification, formal verification, and low-power design.
- Engage directly with chip architects, design leaders, and engineering executives to understand technical requirements, program objectives, and tool environments.
- Develop reusable solution patterns and reference architectures based on successful client engagements.
- Contribute thought leadership around AI-assisted semiconductor design, advanced-node tape-out readiness, chiplets, and multi-die architectures.
Key Selection Criteria
Required
- 15+ years of hands-on ASIC and/or SoC design experience, with deep expertise in at least two areas:
- RTL / microarchitecture
- Design for Test (DFT)
- Physical design
- Functional verification (UVM/SVA)
- Low-power design (CPF/UPF)
- Demonstrated experience in a pre-sales, solution architecture, consulting, or client-facing technical leadership role, ideally within an engineering services, semiconductor, or EDA environment.
- Strong command of major EDA ecosystems, including Synopsys, Cadence, and/or Siemens EDA.
- Experience with advanced semiconductor process nodes, ideally 7nm and below.
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, VLSI Design, or a related technical discipline.
Preferred
- Experience with chiplet architectures, UCIe, and/or multi-die integration.
- Familiarity with AI/ML accelerator architectures, NPUs, and inference-engine design challenges.
- Experience translating highly complex semiconductor engineering requirements into client-facing solutions, architectures, and delivery models.
Confidentiality
This is a confidential executive search. Additional information regarding the organization, reporting structure, and broader mandate will be shared with qualified candidates during the search process.
About Pump Dynamics
Sourced by ZipRecruiter
Industry
Facilities support services
Company size
11 - 50 Employees
Headquarters location
Washougal, WA, US
Year founded
2008