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Cpu Rtl Design Engineer Jobs in Buffalo Grove, IL

Physical Design Engineer

Mundelein, IL · Hybrid

$138K - $142K/yr

Physical Design Engineer (PD/PnR) Location: Bay Area / Austin (Hybrid Job Summary Seeking a ... with RTL, DFT, Power, and Signoff teams to achieve PPA targets. Required Qualifications • ...

New

... Engineering, or related fields * 12+ years of experience in digital design of high-speed SerDes, PHY, or transceiver IPs with proven tapeout experience at 112G PAM4 or higher data rates * Strong RTL ...

PD - IP Lead - Sr Staff, Physical Design

Mundelein, IL · On-site

$138K - $142K/yr

As an Eliyan Sr Staff / Principal Physical Design Engineer, you will be working at a fast-paced ... You will drive the development of cutting-edge ASICs from RTL to GDSII. You will work with a cross ...

What you'll do as a Senior FPGA Engineer at Akuna: We are looking for Senior FPGA Engineers to ... maintain RTL in Verilog/SystemVerilog * Write and maintain verification environments * Design ...

What you'll do as a Senior FPGA Engineer at Akuna: We are looking for Senior FPGA Engineers to ... maintain RTL in Verilog/SystemVerilog * Write and maintain verification environments * Design ...

As an Eliyan Principal Physical Design Engineer, you will be working at a fast-paced early-stage ... You will drive the development of cutting-edge ASICs from RTL to GDSII. You will work with a cross ...

As an Eliyan Principal Physical Design Engineer, you will be working at a fast-paced early-stage ... You will drive the development of cutting-edge ASICs from RTL to GDSII. You will work with a cross ...

FPGA Engineer

Chicago, IL · On-site

$180K - $280K/yr

We are looking for talented hardware engineers with a track record of achievement in any domain ... Develop RTL on the latest FPGAs with modern design flows * Following through into production ...

FPGA Engineer

Elk Grove Village, IL

$128K - $164K/yr

Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded software, System ... Key Responsibilities FPGA Design and Development: Design and develop IP cores and FPGA ...

FPGA Engineer

Chicago, IL

$180K - $280K/yr

We are looking for talented hardware engineers with a track record of achievement in any domain ... Develop RTL on the latest FPGAs with modern design flows * Following through into production ...

FPGA Engineer

Elk Grove Village, IL

$128K - $164K/yr

Apply Now RTL, C/C++, Python, VHDL, Verilog, Tcl, cryptography, hardware, embedded software, System ... Key Responsibilities FPGA Design and Development: Design and develop IP cores and FPGA ...

As an Eliyan Staff DFT Engineer, you will be working at a fast-paced early-stage startup creating ... at the RTL & gate level * General knowledge of digital and AMS circuit design techniques

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Cpu Rtl Design Engineer information

See Buffalo Grove, IL salary details

$41.5K

$90.4K

$162.5K

How much do cpu rtl design engineer jobs pay per year?

As of Jun 16, 2026, the average yearly pay for cpu rtl design engineer in Buffalo Grove, IL is $90,401.00, according to ZipRecruiter salary data. Most workers in this role earn between $69,700.00 and $101,000.00 per year, depending on experience, location, and employer.

What is the difference between Cpu Rtl Design Engineer vs Cpu Verification Engineer?

AspectCpu Rtl Design EngineerCpu Verification Engineer
Primary FocusDesigning and developing RTL code for CPU componentsVerifying and testing RTL designs for correctness
Skills & CertificationsHDL languages (Verilog/VHDL), FPGA/ASIC design experienceHDL, testbench development, simulation tools
Work EnvironmentDesign teams, hardware development labsVerification teams, simulation environments
Industry UsageSemiconductor companies, CPU design firmsASIC/FPGA verification, chip validation

While both roles require HDL knowledge and work within hardware design environments, Cpu Rtl Design Engineers focus on creating the RTL code for CPU components, whereas Cpu Verification Engineers concentrate on testing and validating those designs to ensure functionality and performance.

What are some common challenges faced by CPU RTL Design Engineers when collaborating with verification and architecture teams?

CPU RTL Design Engineers often work closely with both verification and architecture teams to ensure that the design meets functional and performance requirements. A common challenge is ensuring clear communication of design intent and handling feedback from verification regarding corner cases or bugs. Balancing architectural changes with design timelines and maintaining synchronization across multiple teams can be demanding. Successful engineers proactively document their work, participate in regular sync-ups, and are open to iterative improvements based on collaborative feedback.

What are the key skills and qualifications needed to thrive as a CPU RTL Design Engineer, and why are they important?

To thrive as a CPU RTL Design Engineer, you need a strong background in digital logic design, computer architecture, and proficiency in hardware description languages like Verilog or VHDL, typically supported by a degree in electrical or computer engineering. Familiarity with industry-standard EDA tools such as Synopsys or Cadence, and experience with simulation, synthesis, and verification methodologies are essential. Strong problem-solving skills, attention to detail, and effective teamwork are crucial soft skills for success in this role. These competencies enable the accurate implementation, debugging, and optimization of complex CPU designs, ensuring performance and reliability in final hardware products.

What are CPU RTL Design Engineers?

CPU RTL (Register Transfer Level) Design Engineers are specialized hardware engineers who design, implement, and verify the digital logic that forms the core of computer processors. They use hardware description languages like Verilog or VHDL to create and simulate the functional blocks of CPUs, ensuring correct operation and optimal performance. Their work involves close collaboration with architecture, verification, and physical design teams to bring processor designs from conception to silicon. They also debug and optimize designs to meet power, speed, and area goals.
What are popular job titles related to Cpu Rtl Design Engineer jobs in Buffalo Grove, IL? For Cpu Rtl Design Engineer jobs in Buffalo Grove, IL, the most frequently searched job titles are:
What cities near Buffalo Grove, IL are hiring for Cpu Rtl Design Engineer jobs? Cities near Buffalo Grove, IL with the most Cpu Rtl Design Engineer job openings:
Physical Design Engineer

Physical Design Engineer

Futran Solutions

Mundelein, IL • Hybrid

$138K - $142K/yr

Other

Posted 2 days ago


Job description

Job Title: Physical Design Engineer (PD/PnR)

Location: Bay Area / Austin (Hybrid


Job Summary

Seeking a Physical Design Engineer with strong hands-on experience in block-level and top-level Place & Route using Synopsys Fusion Compiler. The candidate will be responsible for implementation, timing closure, low-power integration, and signoff activities for complex SoC designs.

Key Responsibilities

• Perform block-level and top-level Physical Design implementation using Fusion Compiler.

• Drive floorplanning, placement, CTS, routing, and timing closure.

• Execute and analyze Static Timing Analysis (STA) across multiple corners and modes.

• Implement and verify low-power designs using UPF, including isolation, level shifters, retention, and power domain checks.

• Support physical signoff activities such as DRC, LVS, IR drop, and EM analysis.

• Collaborate with RTL, DFT, Power, and Signoff teams to achieve PPA targets.

Required Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.

• Strong experience in Physical Design and PnR flows.

• Hands-on expertise with Synopsys Fusion Compiler.

• Solid understanding of STA, timing closure, and MMMC methodologies.

• Experience with low-power implementation and verification flows.

• Good scripting skills in Tcl, Perl, or Python.

Preferred

• Experience with advanced technology nodes (7nm and below).

• Exposure to full-chip integration and signoff methodologies.

• Strong debugging and problem-solving skills.