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Dft Jobs (NOW HIRING)

Purple Hires Inc

DFT Engineer

Plano, TX · Remote

Lead ASIC DFT Engineer Location: Remote, (Onsite) Duration: Contract Year of Exp: 8+ yrs to 15 yrs. We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and ...

Retym

DFT Engineer

Austin, TX · On-site

As a DFT Engineer you will work closely with all other design teams - backend, verification and analog, fully responsible for defining, implementing, and deploying advanced design-for-test (DFT ...

Intellectt INC

DFT Engineer

Santa Clarita, CA · On-site

Hello, My name is Bipasa, and I'm reaching out from Intellectt Inc. regarding an exciting contract opportunity for a DFT Engineer based in Santa Clara, California with one of our prestigious clients.

VentureSoft Global

DFT Engineer

San Jose, CA · On-site

Principal DFT Engineer-San Jose,CA We are hiring for a Principal DFT Engineer with strong Siemens Tessent experience for onsite opportunity in San Jose, CA. Key DFT Responsibilities & Skills: * Tool ...

Lorven Technologies

DFT Engineer

Santa Clara, CA · On-site

DFT Engineer Location: Santa Clara, CA Required Skills & Qualifications • 5+ years of hands-on experience in DFT and ATPG for SoC or ASIC designs • Strong understanding of DFT fundamentals ...

iFlow Inc

DFT Engineer

Santa Clara, CA · On-site

DFT Engineer Location:Santa Clara CA Duration:Long term Experience:8-15 Years Role Purpose We are hiring a DFT Engineer with hands-on experience in Scan, ATPG, MBIST, or Boundary Scan Key ...

Advanced Micro Devices, Inc

DFT Architect

San Jose, CA · On-site

As a DFT Architect you will drive DFT architecture definitions of Scan, MBIST, PHY, high-speed/high-density IOs, communication controllers and FPGA logics of future AMD products. The role involves ...

Advanced Micro Devices, Inc

DFT Architect

San Jose, CA · On-site

$203K/yr

As a DFT Architect you will drive DFT architecture definitions of Scan, MBIST, PHY, high-speed/high-density IOs, communication controllers and FPGA logics of future AMD products. The role involves ...

Intellectt INC

DFT Engineers

Santa Clara, CA · On-site

DFT Engineers Location: Santa Clara, California We are looking for a DFT / ATPG Engineer with strong experience in SoC/ASIC test methodologies, SCAN, MBIST, ATPG, and IJTAG implementation. The ...

Purple Hires Inc

ASIC DFT Engineer

Plano, TX · Remote

Lead ASIC DFT Engineer Location: Remote, (Onsite) Duration: Contract Year of Exp: 8+ yrs to 15 yrs. We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and ...

Intellectt INC

DFT Engineers

Santa Clarita, CA · On-site

We have an urgent opening for a DFT Engineers position based in Santa Clara, CA with one of our prestigious clients. If you are interested or know someone who might be a good fit, please share your ...

Select Minds LLC

DFT Engineer

Santa Clara, CA · On-site

$65 - $130/hr

Opportunity for advancement DFT Engineer (Design for Test) Location: Santa Clara, CA (Onsite) Employment Type: Long-Term Contract Interview Process: Virtual Interviews Compensation: Based on ...

Eliyan

DFT - Staff DFT Engineer

Mundelein, IL

As an Eliyan Staff DFT Engineer, you will be working at a fast-paced early-stage startup creating technologies that fuel tomorrow's chiplet based systems with best-in-class power, area ...

Reveille Technologies

DFT Engineer

Mountain View, CA · On-site

DFT Engineer (Scan / MBIST / ATPG) Location: Mountain View CA DFT Engineer (Scan / MBIST / ATPG) We are seeking a DFT Engineer with hands-on experience in Scan, MBIST, ATPG generation, and pattern ...

INA Solution Inc

DFT Engineer

San Jose, CA · On-site

$144K - $191K/yr

DFT Engineer San Jose, CA, San Diego, CA, Irvine, CA, Chandler, AZ Required Skills: * Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or ...

Retym

DFT Tech Lead

Austin, TX · On-site

As a DFT Tech Lead you will work closely with all other design teams - backend, vlsi, verification and analog, fully responsible for defining, implementing, and deploying advanced design-for-test ...

Intellectt INC

DFT Engineers

Santa Clara, CA · On-site

DFT Engineers Location: Santa Clara, California : * 5+ years of hands-on experience in DFT and ATPG for SoC or ASIC designs * Strong understanding of DFT fundamentals including controllability ...

Select Minds LLC

DFT Engineer

Santa Clara, CA · On-site

$65 - $130/hr

Opportunity for advancement DFT Engineer (Design for Test) Location: Santa Clara, CA (Onsite) Employment Type: Long-Term Contract Interview Process: Virtual Interviews Compensation: Based on ...

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Dft information

See salary details

$69.5K

$78.1K

$85K

How much do dft jobs pay per year?

As of Aug 9, 2026, the average yearly pay for dft in the United States is $78,100.00, according to ZipRecruiter salary data. Most workers in this role earn between $74,000.00 and $82,000.00 per year, depending on experience, location, and employer.

What is a DFT job?

A DFT job typically refers to a role involving Design for Testability, where professionals develop testing strategies and procedures to ensure the quality and reliability of electronic circuits and systems. It often requires knowledge of testing tools, circuit design, and industry standards, and may involve working with automated testing equipment. The position usually demands technical skills and attention to detail to identify and address potential manufacturing defects.

Is DFT engineering a good career?

DFT engineering, which involves designing and implementing design-for-testability features in integrated circuits, is a specialized field within electronics and semiconductor industries. It offers opportunities in chip design, testing, and quality assurance, often requiring knowledge of digital design, VLSI, and testing tools. The career can be stable and well-paying for those with relevant skills and certifications, with demand driven by advancements in semiconductor technology.

What is the difference between Dft vs Draftsman?

AspectDftDraftsman
Required CredentialsTypically requires a diploma or certification in drafting or engineeringOften requires a diploma or technical training in drafting or architecture
Work EnvironmentWorks in engineering, construction, or manufacturing settingsWorks mainly in architectural or engineering offices
Industry UsageCommonly used in engineering, manufacturing, and construction industriesPrimarily used in architecture and civil engineering sectors
Job FocusDesigning and creating technical drawings for engineering projectsPreparing detailed architectural or structural drawings

In summary, Dft and Draftsman roles share similar skills and work environments, often requiring technical diplomas. Dft typically refers to a broader engineering drafting role, while Draftsman is more focused on architectural drawings. Both are essential in their respective industries for translating concepts into technical plans.

What are the key skills and qualifications needed to thrive as a Design for Test (DFT) engineer?

To thrive as a Design for Test (DFT) Engineer, you need a solid background in digital design, VLSI concepts, and experience with ASIC/FPGA design, typically supported by a degree in electrical or computer engineering. Proficiency with EDA tools such as Synopsys DFT Compiler, Mentor Tessent, and scripting languages like TCL or Python is essential, along with knowledge of test methodologies like scan insertion and ATPG. Strong problem-solving abilities, attention to detail, and effective communication skills help in debugging complex issues and collaborating across teams. These skills are vital for ensuring high-quality, testable hardware designs that meet production and reliability standards.

What are some common challenges faced by DFT engineers when collaborating with design and verification teams?

DFT engineers often encounter challenges ensuring their test structures integrate seamlessly with the main design and verification flows. Balancing test coverage with minimal impact on design performance requires ongoing communication and compromise. Additionally, DFT engineers must frequently align on methodologies and resolve conflicts between testability requirements and design constraints, making cross-functional teamwork essential for success.

What is a DFT engineer?

DFT engineers, or Design for Test engineers, are professionals in the semiconductor industry who specialize in designing and implementing testability features in integrated circuits (ICs) and systems-on-chip (SoCs). Their primary role is to ensure that chips can be efficiently and effectively tested for manufacturing defects after fabrication. This involves adding test structures, developing test methodologies, and working closely with design and verification teams to optimize test coverage and reduce the cost of testing. DFT engineers play a critical role in improving product quality and yield in chip manufacturing.

Is DFT a good place to work?

DFT, as a job title, typically refers to a role such as a Design for Test engineer or a similar technical position. The work environment and job satisfaction depend on the company, industry, and specific role, but these positions often require technical skills and attention to detail. Overall, the quality of the workplace varies and should be evaluated based on company culture, benefits, and career growth opportunities.
More about Dft jobs
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Dft jobs near you
Infographic showing various Dft job openings in the United States as of August 2026, with employment types broken down into 72% Full Time, and 28% Contract. Highlights an 96% In-person, and 4% Remote job distribution, with an average salary of $78,100 per year, or $37.5 per hour.

DFT Engineer

Purple Hires Inc

Plano, TX • Remote

Contractor

Re-posted 10 days ago

Job description

Role: Lead ASIC DFT Engineer
Location: Remote, (Onsite)
Duration: Contract
 
Year of Exp: 8+ yrs to 15 yrs.
 
Job Description:
We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues. The ideal candidate will have strong hands-on expertise in DFT fundamentals, fault models, test coverage, diagnosis, and debug, as well as the ability to evaluate and adopt emerging DFT methodologies and architecture schemes to improve robustness, quality, and yield.
Key Responsibilities:
  • Lead DFT architecture, implementation, verification, and sign-off for complex ASIC and SoC designs.
  • Drive scan architecture, scan insertion, scan chain stitching, and scan compression workflows to achieve high coverage and robust testability.
  • Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon bring-up phases.
  • Perform DFT debug, failure analysis, root-cause investigation, and fault coverage closure for complex silicon issues.
  • Develop and validate DFT constraints, including DFT SDC, timing checks, and DFT-specific timing analysis.
  • Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to resolve integration and implementation issues.
  • Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug.
  • Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration.
  • Review RTL, synthesis, LEC, and physical design impacts on DFT implementation and test quality.
  • Act as a technical escalation point for advanced DFT and post-silicon debug issues.
  • Mentor junior and mid-level DFT engineers and promote best practices in DFT methodology and automation.
  • Develop scripts and automation using TCL, PERL, or Python to improve flow efficiency and debug productivity.
Required Skills & Qualifications:
  • Strong hands-on experience in ASIC DFT with end-to-end ownership.
  • Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.
  • Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.
  • Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.
  • Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.
  • Experience with MBIST implementation and verification; SMS experience preferred.
  • Experience with scan architecture and scan chain stitching; Tessent/SSN experience preferred.
  • Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and physical design implementation.
  • Proven post-silicon debug and silicon bring-up experience.
  • Exposure to large SoC designs, hierarchical DFT flows, and multi-domain integration challenges.
  • Strong communication skills and the ability to work independently with minimal ramp-up.
Preferred Experience:
  • MBIST post-silicon validation.
  • ATPG simulations and fault coverage debug.
  • DFT RTL, DFD, DFT verification, and IP-level DFT integration.
  • DFT SDC creation and DFT timing closure support.
  • Boundary scan, iJTAG, SSN, and design-for-debug methodologies.
  • TCL/PERL scripting for DFT automation, reporting, and debug.
  • Experience working across multiple ASIC technology nodes and complex product development cycles.
  • Familiarity with yield learning, diagnosis, and manufacturing test optimization.