OR · On-site
$170K - $250K/yr
The Role We are seeking a highly experienced Senior Design-for-Test (DFT) Engineer to lead and drive DFT architecture and implementation for complex mixed-signal SOCs. This role requires deep ...
Position Overview We seek a DFT Application Engineer to provide technical support to Intel Foundry Services customers on PDKs, DFT/DFM insertion, and ATPG validation methodologies. This critical role ...
Position Overview We seek a DFT Application Engineer to provide technical support to Intel Foundry Services customers on PDKs, DFT/DFM insertion, and ATPG validation methodologies. This critical role ...
OR · On-site
$190K - $285K/yr
You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a ...
$170K - $250K/yr
You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a ...
$170K - $250K/yr
Collaborate with front-end, verification, and DFT teams to ensure clean handoff and predictable convergence. * Work with external physical design service providers and internal leads to review ...
OR · On-site
$190K - $280K/yr
You will own the full physical design flow-from RTL handoff to GDSII-and collaborate closely with architecture, RTL design, DFT, and packaging teams. This role also involves managing external ...
Test Development Engineer
Canby, OR · On-site
Work with customer design teams to ensure Design for Testability (DFT) requirements are incorporated into PCB designs. * Collaborate with internal test engineers to define test strategies, coverage ...
Test Development Engineer
Canby, OR · On-site
Work with customer design teams to ensure Design for Testability (DFT) requirements are incorporated into PCB designs. * Collaborate with internal test engineers to define test strategies, coverage ...
Work with customer design teams to ensure Design for Testability (DFT) requirements are incorporated into PCB designs. * Collaborate with internal test engineers to define test strategies, coverage ...
Work with customer design teams to ensure Design for Testability (DFT) requirements are incorporated into PCB designs. * Collaborate with internal test engineers to define test strategies, coverage ...
Work with customer design teams to ensure Design for Testability (DFT) requirements are incorporated into PCB designs. * Collaborate with internal test engineers to define test strategies, coverage ...
Quick apply
Work with customer design teams to ensure Design for Testability (DFT) requirements are incorporated into PCB designs. * Collaborate with internal test engineers to define test strategies, coverage ...
Understanding of DFT logic and experience with DFT timing closure for various modes e.g., scan, BIST, etc. * Understanding and timing closure of digital logic/macros in AMS designs/IPs. * Experience ...
Understanding of DFT logic and experience with DFT timing closure for various modes e.g., scan, BIST, etc. * Understanding and timing closure of digital logic/macros in AMS designs/IPs. * Experience ...
DDR Design Engineer
Beaverton, OR · On-site
Exposure to Design For Test, understanding of scan concept and writing DFT friendly RTL. Unified Power Format for simulation, synthesis and electrical rule checking Equivalence checking. Prior ...
DDR Design Engineer
Beaverton, OR · On-site
Exposure to Design For Test, understanding of scan concept and writing DFT friendly RTL. Unified Power Format for simulation, synthesis and electrical rule checking Equivalence checking. Prior ...
ASIC Physical Design Principal Consultant
Hillsboro, OR · On-site
$148K - $152K/yr
Exposure to DFT is preferred. * Analytical and Communication skills. * Planning and Co-ordination skills. * Experience with project management. * Experience and desire to work in a management ...
ASIC Physical Design Principal Consultant
Hillsboro, OR · On-site
$148K - $152K/yr
Exposure to DFT is preferred. * Analytical and Communication skills. * Planning and Co-ordination skills. * Experience with project management. * Experience and desire to work in a management ...
OR · Hybrid
DFT & Block-Level Integration: Skilled in employing best-known methods to optimize and handle DFT structures within block-level physical design implementations. * EDA Tool Proficiency: Expert-level ...
Exposure to Design For Test, understanding of scan concept and writing DFT friendly RTL. Unified Power Format for simulation, synthesis and electrical rule checking Equivalence checking. Prior ...
Exposure to Design For Test, understanding of scan concept and writing DFT friendly RTL. Unified Power Format for simulation, synthesis and electrical rule checking Equivalence checking. Prior ...
Exposure to Design For Test, understanding of scan concept and writing DFT friendly RTL. Unified Power Format for simulation, synthesis and electrical rule checking Equivalence checking. Prior ...
Exposure to Design For Test, understanding of scan concept and writing DFT friendly RTL. Unified Power Format for simulation, synthesis and electrical rule checking Equivalence checking. Prior ...
DDR Design Engineer
Beaverton, OR · On-site
Exposure to Design For Test, understanding of scan concept and writing DFT friendly RTL. Unified Power Format for simulation, synthesis and electrical rule checking Equivalence checking. Prior ...
DDR Design Engineer
Beaverton, OR · On-site
Exposure to Design For Test, understanding of scan concept and writing DFT friendly RTL. Unified Power Format for simulation, synthesis and electrical rule checking Equivalence checking. Prior ...
SoC Design and Verification
Hillsboro, OR · On-site
$148K - $180K/yr
DC, NCSim, Verdi, Spyglass-DFT, LP, TXV, CDC (preferred DC, NC-Sim, and Spyglass). * Experience in clock gating, synthesis, CDC, and ECO process is a PLUS. * Protocol: PCIe (mandatory), Ethernet ...
SoC Design and Verification
Hillsboro, OR · On-site
$148K - $180K/yr
DC, NCSim, Verdi, Spyglass-DFT, LP, TXV, CDC (preferred DC, NC-Sim, and Spyglass). * Experience in clock gating, synthesis, CDC, and ECO process is a PLUS. * Protocol: PCIe (mandatory), Ethernet ...
Timing Design Engineer
Beaverton, OR · On-site
Familiarity with synthesis, DFT and backend related methodology and tools. Strong communication skills are a pre-requisite - you will be collaborating with many diverse groups at Apple. The ideal ...
Timing Design Engineer
Beaverton, OR · On-site
Familiarity with synthesis, DFT and backend related methodology and tools. Strong communication skills are a pre-requisite - you will be collaborating with many diverse groups at Apple. The ideal ...
Familiarity with synthesis, DFT and backend related methodology and tools. Strong communication skills are a pre-requisite - you will be collaborating with many diverse groups at Apple. The ideal ...
Familiarity with synthesis, DFT and backend related methodology and tools. Strong communication skills are a pre-requisite - you will be collaborating with many diverse groups at Apple. The ideal ...
Timing Design Engineer
Beaverton, OR · On-site
... DFT and backend related methodology and tools. Strong communication skills are a pre-requisite. You will be collaborating with many diverse groups at Apple. The ideal candidate will be a self starter ...
Timing Design Engineer
Beaverton, OR · On-site
... DFT and backend related methodology and tools. Strong communication skills are a pre-requisite. You will be collaborating with many diverse groups at Apple. The ideal candidate will be a self starter ...
Dft information
See Oregon salary details
$73.5K - $75K
5% of jobs
$75K - $76.5K
9% of jobs
$76.5K - $78K
6% of jobs
$78.5K is the 25th percentile. Wages below this are outliers.
$78K - $79.4K
10% of jobs
$79.4K - $80.9K
10% of jobs
The median wage is $82.1K / yr.
$80.9K - $82.4K
10% of jobs
$82.4K - $83.9K
10% of jobs
$83.9K - $85.4K
10% of jobs
$85.9K is the 75th percentile. Wages above this are outliers.
$85.4K - $86.9K
6% of jobs
$86.9K - $88.4K
10% of jobs
$88.4K - $89.9K
10% of jobs
$73.5K
$82.6K
$89.9K
How much do dft jobs pay per year?
As of Aug 10, 2026, the average yearly pay for dft in Oregon is $82,573.00, according to ZipRecruiter salary data. Most workers in this role earn between $78,200.00 and $86,700.00 per year, depending on experience, location, and employer.
What is a DFT job?
A DFT job typically refers to a role involving Design for Testability, where professionals develop testing strategies and procedures to ensure the quality and reliability of electronic circuits and systems. It often requires knowledge of testing tools, circuit design, and industry standards, and may involve working with automated testing equipment. The position usually demands technical skills and attention to detail to identify and address potential manufacturing defects.
Is DFT engineering a good career?
DFT engineering, which involves designing and implementing design-for-testability features in integrated circuits, is a specialized field within electronics and semiconductor industries. It offers opportunities in chip design, testing, and quality assurance, often requiring knowledge of digital design, VLSI, and testing tools. The career can be stable and well-paying for those with relevant skills and certifications, with demand driven by advancements in semiconductor technology.
What is the difference between Dft vs Draftsman?
| Aspect | Dft | Draftsman |
|---|---|---|
| Required Credentials | Typically requires a diploma or certification in drafting or engineering | Often requires a diploma or technical training in drafting or architecture |
| Work Environment | Works in engineering, construction, or manufacturing settings | Works mainly in architectural or engineering offices |
| Industry Usage | Commonly used in engineering, manufacturing, and construction industries | Primarily used in architecture and civil engineering sectors |
| Job Focus | Designing and creating technical drawings for engineering projects | Preparing detailed architectural or structural drawings |
In summary, Dft and Draftsman roles share similar skills and work environments, often requiring technical diplomas. Dft typically refers to a broader engineering drafting role, while Draftsman is more focused on architectural drawings. Both are essential in their respective industries for translating concepts into technical plans.
What are the key skills and qualifications needed to thrive as a Design for Test (DFT) engineer?
To thrive as a Design for Test (DFT) Engineer, you need a solid background in digital design, VLSI concepts, and experience with ASIC/FPGA design, typically supported by a degree in electrical or computer engineering. Proficiency with EDA tools such as Synopsys DFT Compiler, Mentor Tessent, and scripting languages like TCL or Python is essential, along with knowledge of test methodologies like scan insertion and ATPG. Strong problem-solving abilities, attention to detail, and effective communication skills help in debugging complex issues and collaborating across teams. These skills are vital for ensuring high-quality, testable hardware designs that meet production and reliability standards.
What are some common challenges faced by DFT engineers when collaborating with design and verification teams?
DFT engineers often encounter challenges ensuring their test structures integrate seamlessly with the main design and verification flows. Balancing test coverage with minimal impact on design performance requires ongoing communication and compromise. Additionally, DFT engineers must frequently align on methodologies and resolve conflicts between testability requirements and design constraints, making cross-functional teamwork essential for success.
What is a DFT engineer?
DFT engineers, or Design for Test engineers, are professionals in the semiconductor industry who specialize in designing and implementing testability features in integrated circuits (ICs) and systems-on-chip (SoCs). Their primary role is to ensure that chips can be efficiently and effectively tested for manufacturing defects after fabrication. This involves adding test structures, developing test methodologies, and working closely with design and verification teams to optimize test coverage and reduce the cost of testing. DFT engineers play a critical role in improving product quality and yield in chip manufacturing.
Is DFT a good place to work?
DFT, as a job title, typically refers to a role such as a Design for Test engineer or a similar technical position. The work environment and job satisfaction depend on the company, industry, and specific role, but these positions often require technical skills and attention to detail. Overall, the quality of the workplace varies and should be evaluated based on company culture, benefits, and career growth opportunities.
What are popular job titles related to Dft jobs in Oregon? For Dft jobs in Oregon, the most frequently searched job titles are:
What job categories do people searching Dft jobs in Oregon look for? The top searched job categories for Dft jobs in Oregon are:
$170K - $250K/yr
Full-time
Medical, Dental, Vision, Life, PTO
Re-posted 11 days ago
Job description
The Role
We are seeking a highly experienced Senior Design-for-Test (DFT) Engineer to lead and drive DFT architecture and implementation for complex mixed-signal SOCs. This role requires deep expertise in memory BIST and TAP controller insertion at RTL, scan insertion and ATPG, and test strategy development across digital and mixed-signal domains. You will play a critical role in ensuring high test coverage, manufacturability, and first-pass silicon success while collaborating closely with design, verification, and physical design teams.
Responsibilities
- Define and implement DFT architecture for mixed-signal SoCs, including scan, MBIST, LBIST, and boundary scan.
- Lead RTL-level DFT insertion, scan chain insertion and optimization, test point insertion, and low-power DFT methodologies.
- Own ATPG flow development and execution by generating high-quality stuck-at, transition, and path delay test patterns. Drive coverage closure and pattern optimization and debug pattern failure and silicon correlation.
- Develop and integrate DFT strategies for mixed-signal blocks, including wrapper-based approaches, and analog test interfaces and BIST solutions.
- Collaborate with RTL, DV, and PD teams to ensure clean DFT integration at RTL and gate-level, and timing and physical constraints alignment (scan reordering, compression, etc.).
- Drive DFT verification and signoff, including Scan/ATPG coverage metrics, DRC/Lint checks (DFT rule compliance), gate-level simulation and pattern validation.
- Support bring-up and silicon debug activities by analyzing tester failures, yield issues, and ATPG pattern correlation with silicon behavior.
- Contribute to methodology development, automation, and flow improvements.
Qualifications
- B.S. or M.S. in Electrical Engineering or related field.
- 7+ years of experience in DFT for complex SoCs.
- Strong hands-on experience with RTL DFT insertion (scan, compression, test points), and ATPG tools and flows.
- Deep understanding of scan architectures, compression techniques, fault models (stuck-at, transition, bridging, path delay), coverage analysis and closure strategies.
- Experience with low-power DFT techniques.
- Familiarity with mixed-signal integration challenges and test methodologies.
- Strong debugging skills across RTL, gate-level, and silicon.
Nice to Have
- Experience with MBIST/LBIST implementation and memory repair flows.
- Knowledge of IEEE 1149.x (JTAG/boundary scan) standards.
- Experience with multi-voltage domain and power-aware DFT.
- Exposure to physical design impacts on DFT (scan chain reordering, congestion, timing).
- Scripting experience for automation.
- Experience in high-speed interfaces (SerDes) or RF/mixed-signal SoCs.
- Prior involvement in A0 silicon bring-up and yield ramp.
- Experience working in cross-functional, geographically distributed teams.
Compensation and Benefits:
- Base salary range for this role is $170,000 - $250,000 + equity in the company
- Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
- Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks
About K2 Space
Sourced by ZipRecruiter
Industry
Guided missile and space vehicle manufacturing
Company size
11 - 50 Employees
Headquarters location
Los Angeles, CA, US
Year founded
2022