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Dft Jobs in Oregon (NOW HIRING)

K2 Space

Senior DFT Engineer

OR · On-site +1

$170K - $250K/yr

The Role We are seeking a highly experienced Senior Design-for-Test (DFT) Engineer to lead and drive DFT architecture and implementation for complex mixed-signal SOCs. This role requires deep ...

Intel

DFT Application Engineer

Hillsboro, OR · On-site

Position Overview We seek a DFT Application Engineer to provide technical support to Intel Foundry Services customers on PDKs, DFT/DFM insertion, and ATPG validation methodologies. This critical role ...

K2 Space

Principal ASIC Design Verification Engineer

OR · On-site +1

$190K - $285K/yr

You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a ...

K2 Space

Senior ASIC Physical Design Engineer

OR · On-site +1

$170K - $250K/yr

Collaborate with front-end, verification, and DFT teams to ensure clean handoff and predictable convergence. * Work with external physical design service providers and internal leads to review ...

K2 Space

Senior ASIC Design Verification Engineer

OR · On-site +1

$170K - $250K/yr

You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a ...

K2 Space

Principal ASIC Physical Design Engineer

OR · On-site +1

$190K - $280K/yr

You will own the full physical design flow-from RTL handoff to GDSII-and collaborate closely with architecture, RTL design, DFT, and packaging teams. This role also involves managing external ...

Milegon LLC

Test Development Engineer

Canby, OR

Work with customer design teams to ensure Design for Testability (DFT) requirements are incorporated into PCB designs. * Collaborate with internal test engineers to define test strategies, coverage ...

QuantumClean

Electrical Engineer

Hillsboro, OR · On-site

Participate in Design for Manufacturing (DFM), Design for Test (DFT), and Design for Reliability (DFR) reviews. * Support electrical validation, verification, qualification, and production testing.

Nvidia

Senior ASIC Timing Engineer

Hillsboro, OR · Hybrid

Understanding of DFT logic and experience with DFT timing closure for various modes e.g., scan, BIST, etc. * Understanding and timing closure of digital logic/macros in AMS designs/IPs. * Experience ...

Microsoft

Senior Debug Tools Engineer

Hillsboro, OR · On-site

$113K - $156K/yr

Partner closely with silicon architecture, DFT, firmware, validation, platform, and operating system teams to investigate complex hardware-software interactions, root-cause issues, and drive ...

Addium Inc

Senior Electrical Engineer

Portland, OR · On-site

$130K - $140K/yr

Partner with contract manufacturers on DFM/DFT reviews and drive designs through EVT, DVT, and PVT gates. * Assess the technical competence of EE candidates and less experienced engineers, providing ...

Addium Inc.

Senior Electrical Engineer

Portland, OR · On-site

$130K - $140K/yr

Partner with contract manufacturers on DFM/DFT reviews and drive designs through EVT, DVT, and PVT gates. * Assess the technical competence of EE candidates and less experienced engineers, providing ...

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Dft information

See Oregon salary details

$73.5K

$82.6K

$89.9K

How much do dft jobs pay per year?

As of Sep 12, 2026, the average yearly pay for dft in Oregon is $82,573.00, according to ZipRecruiter salary data. Most workers in this role earn between $78,200.00 and $86,700.00 per year, depending on experience, location, and employer.

What is a DFT engineer?

DFT engineers, or Design for Test engineers, are professionals in the semiconductor industry who specialize in designing and implementing testability features in integrated circuits (ICs) and systems-on-chip (SoCs). Their primary role is to ensure that chips can be efficiently and effectively tested for manufacturing defects after fabrication. This involves adding test structures, developing test methodologies, and working closely with design and verification teams to optimize test coverage and reduce the cost of testing. DFT engineers play a critical role in improving product quality and yield in chip manufacturing.

What are the key skills and qualifications needed to thrive as a Design for Test (DFT) engineer?

To thrive as a Design for Test (DFT) Engineer, you need a solid background in digital design, VLSI concepts, and experience with ASIC/FPGA design, typically supported by a degree in electrical or computer engineering. Proficiency with EDA tools such as Synopsys DFT Compiler, Mentor Tessent, and scripting languages like TCL or Python is essential, along with knowledge of test methodologies like scan insertion and ATPG. Strong problem-solving abilities, attention to detail, and effective communication skills help in debugging complex issues and collaborating across teams. These skills are vital for ensuring high-quality, testable hardware designs that meet production and reliability standards.

What are some common challenges faced by DFT engineers when collaborating with design and verification teams?

DFT engineers often encounter challenges ensuring their test structures integrate seamlessly with the main design and verification flows. Balancing test coverage with minimal impact on design performance requires ongoing communication and compromise. Additionally, DFT engineers must frequently align on methodologies and resolve conflicts between testability requirements and design constraints, making cross-functional teamwork essential for success.

What is the difference between Dft vs Draftsman?

AspectDftDraftsman
Required CredentialsTypically requires a diploma or certification in drafting or engineeringOften requires a diploma or technical training in drafting or architecture
Work EnvironmentWorks in engineering, construction, or manufacturing settingsWorks mainly in architectural or engineering offices
Industry UsageCommonly used in engineering, manufacturing, and construction industriesPrimarily used in architecture and civil engineering sectors
Job FocusDesigning and creating technical drawings for engineering projectsPreparing detailed architectural or structural drawings

In summary, Dft and Draftsman roles share similar skills and work environments, often requiring technical diplomas. Dft typically refers to a broader engineering drafting role, while Draftsman is more focused on architectural drawings. Both are essential in their respective industries for translating concepts into technical plans.

Is DFT a good career?

A DFT (Design for Test) engineer specializes in developing testing methods for electronic circuits and systems, often requiring knowledge of digital and analog testing techniques, CAD tools, and industry standards. It can be a stable career with opportunities in electronics manufacturing, semiconductor, and technology companies, especially for those with strong technical skills and certifications. The role typically involves problem-solving, attention to detail, and staying current with testing technologies.

Is DFT a good place to work?

DFT, as a job title, typically refers to a role such as a Design for Test engineer or a similar technical position. The work environment and job satisfaction depend on the company, industry, and specific role, but these positions often require technical skills and attention to detail. Overall, the suitability of DFT as a workplace varies based on individual preferences and organizational culture.

What are popular job titles related to Dft jobs in Oregon?

For Dft jobs in Oregon, the most frequently searched job titles are:

What job categories do people searching Dft jobs in Oregon look for?

The top searched job categories for Dft jobs in Oregon are:

Dft jobs near you
Infographic showing various Dft job openings in Oregon as of September 2026, with employment types broken down into 1% Internship, 76% Full Time, 21% Part Time, and 2% Contract. Highlights an 91% Physical, 5% Hybrid, and 4% Remote job distribution, with an average salary of $82,573 per year, or $39.7 per hour.

Senior DFT Engineer

OR • On-site, Remote

K2 Space
Guided Missile and Space Vehicle Manufacturing • 11 - 50 employees
Learn more about K2 Spaceexternal

$170K - $250K/yr

Full-time

Medical, Dental, Vision, Life, PTO

Re-posted 14 days ago

Job description

The Role 

We are seeking a highly experienced Senior Design-for-Test (DFT) Engineer to lead and drive DFT architecture and implementation for complex mixed-signal SOCs. This role requires deep expertise in memory BIST and TAP controller insertion at RTL, scan insertion and ATPG, and test strategy development across digital and mixed-signal domains. You will play a critical role in ensuring high test coverage, manufacturability, and first-pass silicon success while collaborating closely with design, verification, and physical design teams.  

Responsibilities 

  • Define and implement DFT architecture for mixed-signal SoCs, including scan, MBIST, LBIST, and boundary scan. 
  • Lead RTL-level DFT insertion, scan chain insertion and optimization, test point insertion, and low-power DFT methodologies. 
  • Own ATPG flow development and execution by generating high-quality stuck-at, transition, and path delay test patterns. Drive coverage closure and pattern optimization and debug pattern failure and silicon correlation.  
  • Develop and integrate DFT strategies for mixed-signal blocks, including wrapper-based approaches, and analog test interfaces and BIST solutions. 
  • Collaborate with RTL, DV, and PD teams to ensure clean DFT integration at RTL and gate-level, and timing and physical constraints alignment (scan reordering, compression, etc.). 
  • Drive DFT verification and signoff, including Scan/ATPG coverage metrics, DRC/Lint checks (DFT rule compliance), gate-level simulation and pattern validation. 
  • Support bring-up and silicon debug activities by analyzing tester failures, yield issues, and ATPG pattern correlation with silicon behavior. 
  • Contribute to methodology development, automation, and flow improvements. 

Qualifications 

  • B.S. or M.S. in Electrical Engineering or related field. 
  • 7+ years of experience in DFT for complex SoCs. 
  • Strong hands-on experience with RTL DFT insertion (scan, compression, test points), and ATPG tools and flows. 
  • Deep understanding of scan architectures, compression techniques, fault models (stuck-at, transition, bridging, path delay), coverage analysis and closure strategies. 
  • Experience with low-power DFT techniques. 
  • Familiarity with mixed-signal integration challenges and test methodologies. 
  • Strong debugging skills across RTL, gate-level, and silicon. 

Nice to Have 

  • Experience with MBIST/LBIST implementation and memory repair flows. 
  • Knowledge of IEEE 1149.x (JTAG/boundary scan) standards. 
  • Experience with multi-voltage domain and power-aware DFT. 
  • Exposure to physical design impacts on DFT (scan chain reordering, congestion, timing). 
  • Scripting experience for automation. 
  • Experience in high-speed interfaces (SerDes) or RF/mixed-signal SoCs. 
  • Prior involvement in A0 silicon bring-up and yield ramp. 
  • Experience working in cross-functional, geographically distributed teams.  

Compensation and Benefits:

  • Base salary range for this role is $170,000 - $250,000 + equity in the company
  • Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
  • Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks
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About K2 Space

Sourced by ZipRecruiter

Industry

Guided missile and space vehicle manufacturing

Company size

11 - 50 Employees

Headquarters location

Los Angeles, CA, US

Year founded

2022

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