Position Overview We seek a DFT Application Engineer to provide technical support to Intel Foundry Services customers on PDKs, DFT/DFM insertion, and ATPG validation methodologies. This critical role ...
Position Overview We seek a DFT Application Engineer to provide technical support to Intel Foundry Services customers on PDKs, DFT/DFM insertion, and ATPG validation methodologies. This critical role ...
OR · On-site
$170K - $250K/yr
The Role We are seeking a highly experienced Senior Design-for-Test (DFT) Engineer to lead and drive DFT architecture and implementation for complex mixed-signal SOCs. This role requires deep ...
Senior Test Engineer
Hillsboro, OR · On-site
Collaborate with design, DFT, product, and manufacturing teams to support scan test readiness, coverage closure, and issue resolution. * Gain exposure to product domains such as high-performance ...
Senior Test Engineer
Hillsboro, OR · On-site
Collaborate with design, DFT, product, and manufacturing teams to support scan test readiness, coverage closure, and issue resolution. * Gain exposure to product domains such as high-performance ...
OR · On-site
$190K - $285K/yr
You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a ...
Product Development Engineer - Scan Diagnostics
$141K - $269K/yr
Develop and optimize tools, methods, and flows for Design for Test (DFT), diagnostics, and yield analysis. * Collaborate with external vendors and internal teams to establish standard industry ...
Product Development Engineer - Scan Diagnostics
$141K - $269K/yr
Develop and optimize tools, methods, and flows for Design for Test (DFT), diagnostics, and yield analysis. * Collaborate with external vendors and internal teams to establish standard industry ...
$170K - $250K/yr
Collaborate with front-end, verification, and DFT teams to ensure clean handoff and predictable convergence. * Work with external physical design service providers and internal leads to review ...
$170K - $250K/yr
You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a ...
$190K - $280K/yr
You will own the full physical design flow-from RTL handoff to GDSII-and collaborate closely with architecture, RTL design, DFT, and packaging teams. This role also involves managing external ...
Work with customer design teams to ensure Design for Testability (DFT) requirements are incorporated into PCB designs. * Collaborate with internal test engineers to define test strategies, coverage ...
Work with customer design teams to ensure Design for Testability (DFT) requirements are incorporated into PCB designs. * Collaborate with internal test engineers to define test strategies, coverage ...
Test Development Engineer
Canby, OR · On-site
Work with customer design teams to ensure Design for Testability (DFT) requirements are incorporated into PCB designs. * Collaborate with internal test engineers to define test strategies, coverage ...
Test Development Engineer
Canby, OR · On-site
Work with customer design teams to ensure Design for Testability (DFT) requirements are incorporated into PCB designs. * Collaborate with internal test engineers to define test strategies, coverage ...
Work with customer design teams to ensure Design for Testability (DFT) requirements are incorporated into PCB designs. * Collaborate with internal test engineers to define test strategies, coverage ...
Quick apply
Work with customer design teams to ensure Design for Testability (DFT) requirements are incorporated into PCB designs. * Collaborate with internal test engineers to define test strategies, coverage ...
Understanding of DFT logic and experience with DFT timing closure for various modes e.g., scan, BIST, etc. * Understanding and timing closure of digital logic/macros in AMS designs/IPs. * Experience ...
Understanding of DFT logic and experience with DFT timing closure for various modes e.g., scan, BIST, etc. * Understanding and timing closure of digital logic/macros in AMS designs/IPs. * Experience ...
ASIC Physical Design Principal Consultant
Hillsboro, OR · On-site
$148K - $152K/yr
Exposure to DFT is preferred. * Analytical and Communication skills. * Planning and Co-ordination skills. * Experience with project management. * Experience and desire to work in a management ...
ASIC Physical Design Principal Consultant
Hillsboro, OR · On-site
$148K - $152K/yr
Exposure to DFT is preferred. * Analytical and Communication skills. * Planning and Co-ordination skills. * Experience with project management. * Experience and desire to work in a management ...
DDR Design Engineer
Beaverton, OR · On-site
Exposure to Design For Test, understanding of scan concept and writing DFT friendly RTL. Unified Power Format for simulation, synthesis and electrical rule checking Equivalence checking. Prior ...
DDR Design Engineer
Beaverton, OR · On-site
Exposure to Design For Test, understanding of scan concept and writing DFT friendly RTL. Unified Power Format for simulation, synthesis and electrical rule checking Equivalence checking. Prior ...
Exposure to Design For Test, understanding of scan concept and writing DFT friendly RTL. Unified Power Format for simulation, synthesis and electrical rule checking Equivalence checking. Prior ...
Exposure to Design For Test, understanding of scan concept and writing DFT friendly RTL. Unified Power Format for simulation, synthesis and electrical rule checking Equivalence checking. Prior ...
DDR Design Engineer
Beaverton, OR · On-site
Exposure to Design For Test, understanding of scan concept and writing DFT friendly RTL. Unified Power Format for simulation, synthesis and electrical rule checking Equivalence checking. Prior ...
DDR Design Engineer
Beaverton, OR · On-site
Exposure to Design For Test, understanding of scan concept and writing DFT friendly RTL. Unified Power Format for simulation, synthesis and electrical rule checking Equivalence checking. Prior ...
Exposure to Design For Test, understanding of scan concept and writing DFT friendly RTL. Unified Power Format for simulation, synthesis and electrical rule checking Equivalence checking. Prior ...
Exposure to Design For Test, understanding of scan concept and writing DFT friendly RTL. Unified Power Format for simulation, synthesis and electrical rule checking Equivalence checking. Prior ...
Understanding of DFT logic and hands-on experience in design closure. * Expertise in analyzing and converging crosstalk delay, noise glitch, and electrical/manufacturing rules in deep-sub micron ...
Understanding of DFT logic and hands-on experience in design closure. * Expertise in analyzing and converging crosstalk delay, noise glitch, and electrical/manufacturing rules in deep-sub micron ...
OR · Hybrid
DFT & Block-Level Integration: Skilled in employing best-known methods to optimize and handle DFT structures within block-level physical design implementations. * EDA Tool Proficiency: Expert-level ...
SoC Design and Verification
$148K - $180K/yr
DC, NCSim, Verdi, Spyglass-DFT, LP, TXV, CDC (preferred DC, NC-Sim, and Spyglass). * Experience in clock gating, synthesis, CDC, and ECO process is a PLUS. * Protocol: PCIe (mandatory), Ethernet ...
SoC Design and Verification
$148K - $180K/yr
DC, NCSim, Verdi, Spyglass-DFT, LP, TXV, CDC (preferred DC, NC-Sim, and Spyglass). * Experience in clock gating, synthesis, CDC, and ECO process is a PLUS. * Protocol: PCIe (mandatory), Ethernet ...
Dft information
See Oregon salary details
$73.5K - $75K
5% of jobs
$75K - $76.5K
9% of jobs
$76.5K - $78K
6% of jobs
$78.5K is the 25th percentile. Wages below this are outliers.
$78K - $79.4K
10% of jobs
$79.4K - $80.9K
10% of jobs
The median wage is $82.1K / yr.
$80.9K - $82.4K
10% of jobs
$82.4K - $83.9K
10% of jobs
$83.9K - $85.4K
10% of jobs
$85.9K is the 75th percentile. Wages above this are outliers.
$85.4K - $86.9K
6% of jobs
$86.9K - $88.4K
10% of jobs
$88.4K - $89.9K
10% of jobs
$73.5K
$82.6K
$89.9K
How much do dft jobs pay per year?
As of Jul 20, 2026, the average yearly pay for dft in Oregon is $82,573.00, according to ZipRecruiter salary data. Most workers in this role earn between $78,200.00 and $86,700.00 per year, depending on experience, location, and employer.
What is the salary of DFT engineer in Nvidia?
The salary of a DFT (Design for Test) engineer at Nvidia typically ranges from $100,000 to $150,000 annually, depending on experience, location, and specific role responsibilities. Nvidia offers competitive compensation packages that may include bonuses and stock options, especially for engineers with specialized skills in verification and testing tools.
Is DFT a good career?
A DFT (Design for Test) engineer specializes in developing testing methods for electronic devices, often requiring knowledge of circuit design and testing tools. It can be a stable career with opportunities in electronics manufacturing and semiconductor industries, especially for those with technical skills and relevant certifications. Job prospects depend on industry demand and individual expertise.
What is the difference between Dft vs Draftsman?
| Aspect | Dft | Draftsman |
|---|---|---|
| Required Credentials | Typically requires a diploma or certification in drafting or engineering | Often requires a diploma or technical training in drafting or architecture |
| Work Environment | Works in engineering, construction, or manufacturing settings | Works mainly in architectural or engineering offices |
| Industry Usage | Commonly used in engineering, manufacturing, and construction industries | Primarily used in architecture and civil engineering sectors |
| Job Focus | Designing and creating technical drawings for engineering projects | Preparing detailed architectural or structural drawings |
In summary, Dft and Draftsman roles share similar skills and work environments, often requiring technical diplomas. Dft typically refers to a broader engineering drafting role, while Draftsman is more focused on architectural drawings. Both are essential in their respective industries for translating concepts into technical plans.
What are ftp jobs?
FTP jobs refer to positions that involve managing or working with File Transfer Protocol (FTP) servers, which are used to transfer files over a network. These roles often require knowledge of network protocols, server management, and security practices, and may involve tasks like uploading, downloading, and maintaining files on remote servers.
What are the key skills and qualifications needed to thrive as a Design for Test (DFT) Engineer, and why are they important?
To thrive as a Design for Test (DFT) Engineer, you need a solid background in digital design, VLSI concepts, and experience with ASIC/FPGA design, typically supported by a degree in electrical or computer engineering. Proficiency with EDA tools such as Synopsys DFT Compiler, Mentor Tessent, and scripting languages like TCL or Python is essential, along with knowledge of test methodologies like scan insertion and ATPG. Strong problem-solving abilities, attention to detail, and effective communication skills help in debugging complex issues and collaborating across teams. These skills are vital for ensuring high-quality, testable hardware designs that meet production and reliability standards.
What are some common challenges faced by DFT (Design for Test) engineers when collaborating with design and verification teams?
DFT engineers often encounter challenges ensuring their test structures integrate seamlessly with the main design and verification flows. Balancing test coverage with minimal impact on design performance requires ongoing communication and compromise. Additionally, DFT engineers must frequently align on methodologies and resolve conflicts between testability requirements and design constraints, making cross-functional teamwork essential for success.
What is DFT role?
A DFT (Design for Test) engineer is responsible for designing integrated circuits and systems to facilitate testing and fault detection. They develop test strategies, create test patterns, and ensure manufacturability and reliability of electronic components, often using specialized tools and industry standards. The role requires knowledge of digital design, testing methodologies, and sometimes automation tools.
What are DFT engineers?
DFT engineers, or Design for Test engineers, are professionals in the semiconductor industry who specialize in designing and implementing testability features in integrated circuits (ICs) and systems-on-chip (SoCs). Their primary role is to ensure that chips can be efficiently and effectively tested for manufacturing defects after fabrication. This involves adding test structures, developing test methodologies, and working closely with design and verification teams to optimize test coverage and reduce the cost of testing. DFT engineers play a critical role in improving product quality and yield in chip manufacturing.
What are popular job titles related to Dft jobs in Oregon? For Dft jobs in Oregon, the most frequently searched job titles are:
What job categories do people searching Dft jobs in Oregon look for? The top searched job categories for Dft jobs in Oregon are:
Intel rating
8.7
Based on 147 frontline employees who took The Breakroom Quiz
11th of 143 rated electronics manufacturers
Job description
Job Details:Job Description:
About Intel Foundry Services
Intel Foundry is a systems foundry dedicated to transforming the global semiconductor industry by delivering cutting-edge silicon process and packaging technology leadership for the AI era. With a focus on scalability, AI advancement, and shaping the future, we provide an unparalleled blend of an industry-leading technology, a rich IP portfolio, a world-class design ecosystem, and an operationally resilient global manufacturing supply chain.
Position Overview
We seek a DFT Application Engineer to provide technical support to Intel Foundry Services customers on PDKs, DFT/DFM insertion, and ATPG validation methodologies. This critical role supports Aerospace, Defense, and Government (ADG) customers in achieving successful tape-outs while ensuring the highest quality standards through comprehensive DFT solutions and customer engagement.
Key Responsibilities
Customer Technical Support & Collaboration
- Provide comprehensive DFT tool/flow/methodology support to address customer issues and challenges, ensuring successful tape-outs and maximum customer satisfaction
- Work closely with internal Intel teams and external stakeholders including foundry customers' design teams, IP providers, and EDA vendors to resolve complex technical issues
- Deliver customer-facing technical support and guidance on DFT implementation strategies
DFT Methodology & Quality Leadership
- Drive quality improvements in ASIC DFT/DFM and ATPG validation methodology, capability/flow, and documentation for both block-level and SoC-level implementations
- Collaborate with RTL and Hard IP designers on DFT/DFM implementation methodology and work with physical designers on DFT/DFM physical implementation, validation, and timing signoff
- Develop and optimize DFT insertion flows for advanced CMOS processes and multi-die designs
Technical Content Development & Training
- Develop application notes, comprehensive documentation, and deliver technical training presentations to customers and internal teams
- Create best practice guidelines and methodology documentation for DFT implementation across various design complexities
- Support knowledge transfer and capability building for both internal teams and customer organizations
Essential Skills & Attributes
- Customer-Focused:Strong customer-oriented attitude and mindset with commitment to customer success
- Self-Motivated:Self-driven and results-oriented with ability to manage multiple complex tasks effectively
- Collaborative:Excellent teamwork skills to drive innovative solutions for customer design implementation challenges
- Analytical:Strong analytical problem-solving capabilities for complex DFT challenges
- Communication:Effective communication skills with experience in collaboration, active listening, and providing constructive technical feedback
The Minimum qualifications are required to be considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications
- US Citizenship required
- Ability to obtain US Government Security Clearance
- Bachelor's degree in Electrical Engineering, Computer Engineering, or STEM-related field
- 3+ years of experience with advanced CMOS processes (22nm and below)
- 3+ years of combined experience in the following: implementing ASIC DFT/DFM insertion (MBIST, LBIST, SCAN, JTAG) at both ASIC design block level and full chip level, including ATPG validation and DFT timing/signoff at SOC level
- 2+ years of experience in one or more of the following scripting languages (Python, Perl, Tcl, and/or shell scripting)
Preferred Qualifications
- Active US Government Security Clearance with a minimum of Secret Level.
- Post-graduate degree in Electrical/Computer Engineering or STEM-related field
- Hands-on experience in Design Implementation and methodology (ASIC design, Fullchip Integration, Design Signoff, LVS, DRC, DFX/DFM, Reliability
- Proficiency with major EDA tools for MBIST insertion, hierarchical SCAN and JTAG insertion, DFT constraint generation and ATPG validation for single die and multi-die designs
- Experience building/developing quality DFT/DFX insertion flow and ATPG validation flow
- Experience providing technical direction to engineering teams and customer support
- Customer-facing experience in technical roles
- Experience with state-of-the-art process technology (7nm and below) and PDK-based technology evaluation
What We Offer
- Opportunity to work with cutting-edge DFT technologies for aerospace, defense, and government applications
- Direct customer engagement and technical leadership in advanced semiconductor design
- Access to Intel's most advanced foundry technologies and comprehensive EDA tool suites
- Competitive compensation
- Professional development in DFT methodologies and foundry services
- Direct impact on national security through advanced semiconductor technology solutions
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
About Intel
Sourced by ZipRecruiter
Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth
Industry
Manufacturing
Company size
10,000+ Employees
Headquarters location
Santa Clara, CA, US
Year founded
1968