RTL Design Engineer
$141K/yr
If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. This is an exciting position in the world class ...
RTL Design Engineer
$141K/yr
If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. This is an exciting position in the world class ...
RTL Design Engineer
$141K/yr
If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. This is an exciting position in the world class ...
RTL Design Engineer
$141K/yr
If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. This is an exciting position in the world class ...
RTL Design Engineer
Beaverton, OR · On-site
If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. This is an exciting position in the world class ...
RTL Design Engineer
Beaverton, OR · On-site
If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. This is an exciting position in the world class ...
RTL Design Engineer
Hillsboro, OR · On-site
$105K - $200K/yr
Develops the logic design, register transfer level (RTL) coding, and simulation for a CPU required to generate cell libraries, functional units, and the CPU IP block for integration in full chip ...
RTL Design Engineer
Hillsboro, OR · On-site
$105K - $200K/yr
Develops the logic design, register transfer level (RTL) coding, and simulation for a CPU required to generate cell libraries, functional units, and the CPU IP block for integration in full chip ...
RTL Design Engineer
Beaverton, OR · On-site
If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. This is an exciting position in the world class ...
RTL Design Engineer
Beaverton, OR · On-site
If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. This is an exciting position in the world class ...
FPGA/RTL Design Engineer - III (W2 Only)
$134K - $184K/yr
FPGA/RTL Design Engineer - III Location: Hillsboro, OR Duration: 4 + Months This is a senior RTL design engineer position. Primary responsibilities include: Working with IP designers and DFx ...
FPGA/RTL Design Engineer - III (W2 Only)
$134K - $184K/yr
FPGA/RTL Design Engineer - III Location: Hillsboro, OR Duration: 4 + Months This is a senior RTL design engineer position. Primary responsibilities include: Working with IP designers and DFx ...
As a CPU RTL Logic Design Engineer your responsibilities will include but are not limited to: Collaborates, drives and develops logic design, register transfer level (RTL) coding, and simulation for ...
As a CPU RTL Logic Design Engineer your responsibilities will include but are not limited to: Collaborates, drives and develops logic design, register transfer level (RTL) coding, and simulation for ...
Senior ASIC Design Engineer
Beaverton, OR · On-site
Sr/ ASIC Design Engineer (5+ Years of Experience) DESCRIPTION OF POSITION/DUTIES - * Architect a ... Run LINT and CDC checks on the RTL code and fix accordingly. * Assist with synthesis and FPGA ...
Senior ASIC Design Engineer
Beaverton, OR · On-site
Sr/ ASIC Design Engineer (5+ Years of Experience) DESCRIPTION OF POSITION/DUTIES - * Architect a ... Run LINT and CDC checks on the RTL code and fix accordingly. * Assist with synthesis and FPGA ...
... RTL design to target power, performance, area and timing goals • Verification - support the verification team in test bench development, formal methods, and simulation/emulation for functional ...
... RTL design to target power, performance, area and timing goals • Verification - support the verification team in test bench development, formal methods, and simulation/emulation for functional ...
... RTL design to target power, performance, area and timing goals • Verification - support the verification team in test bench development, formal methods, and simulation/emulation for functional ...
... RTL design to target power, performance, area and timing goals • Verification - support the verification team in test bench development, formal methods, and simulation/emulation for functional ...
... RTL design to target power, performance, area and timing goals • Verification - support the verification team in test bench development, formal methods, and simulation/emulation for functional ...
... RTL design to target power, performance, area and timing goals • Verification - support the verification team in test bench development, formal methods, and simulation/emulation for functional ...
FE RTL Infrastructure - CAD Engineer
Beaverton, OR · On-site
$172K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
FE RTL Infrastructure - CAD Engineer
Beaverton, OR · On-site
$172K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
... RTL design to target power, performance, area and timing goals • Verification - support the verification team in test bench development, formal methods, and simulation/emulation for functional ...
... RTL design to target power, performance, area and timing goals • Verification - support the verification team in test bench development, formal methods, and simulation/emulation for functional ...
FE RTL Infrastructure - CAD Engineer
Beaverton, OR · On-site
$172K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
FE RTL Infrastructure - CAD Engineer
Beaverton, OR · On-site
$172K/yr
Description As a Front-End (FE) RTL Infrastructure - CAD Engineer, you will play a major role in developing and supporting a reliable infrastructure and work environments that design and verification ...
... RTL design to target power, performance, area and timing goals • Verification - support the verification team in test bench development, formal methods, and simulation/emulation for functional ...
... RTL design to target power, performance, area and timing goals • Verification - support the verification team in test bench development, formal methods, and simulation/emulation for functional ...
... RTL design to target power, performance, area and timing goals • Verification - support the verification team in test bench development, formal methods, and simulation/emulation for functional ...
... RTL design to target power, performance, area and timing goals • Verification - support the verification team in test bench development, formal methods, and simulation/emulation for functional ...
CPU Cache Microarchitect/RTL Engineer
$184K - $324K/yr
... RTL design to target power, performance, area and timing goals • Verification - support the verification team in test bench development, formal methods, and simulation/emulation for functional ...
CPU Cache Microarchitect/RTL Engineer
$184K - $324K/yr
... RTL design to target power, performance, area and timing goals • Verification - support the verification team in test bench development, formal methods, and simulation/emulation for functional ...
CPU Cache Microarchitect/RTL Engineer
$184K - $324K/yr
... RTL design to target power, performance, area and timing goals • Verification - support the verification team in test bench development, formal methods, and simulation/emulation for functional ...
CPU Cache Microarchitect/RTL Engineer
$184K - $324K/yr
... RTL design to target power, performance, area and timing goals • Verification - support the verification team in test bench development, formal methods, and simulation/emulation for functional ...
CPU Cache Microarchitect/RTL Engineer
$184K - $324K/yr
... RTL design to target power, performance, area and timing goals • Verification - support the verification team in test bench development, formal methods, and simulation/emulation for functional ...
CPU Cache Microarchitect/RTL Engineer
$184K - $324K/yr
... RTL design to target power, performance, area and timing goals • Verification - support the verification team in test bench development, formal methods, and simulation/emulation for functional ...
CPU Cache Microarchitect/RTL Engineer
$184K - $324K/yr
... RTL design to target power, performance, area and timing goals • Verification - support the verification team in test bench development, formal methods, and simulation/emulation for functional ...
CPU Cache Microarchitect/RTL Engineer
$184K - $324K/yr
... RTL design to target power, performance, area and timing goals • Verification - support the verification team in test bench development, formal methods, and simulation/emulation for functional ...
Rtl Design information
See Oregon salary details
$85.1K - $94.9K
0% of jobs
$94.9K - $104.7K
0% of jobs
$104.7K - $114.5K
1% of jobs
$114.5K - $124.3K
0% of jobs
$124.3K - $134.1K
0% of jobs
$138.2K is the 25th percentile. Wages below this are outliers.
$134.1K - $143.9K
57% of jobs
$148.2K is the 75th percentile. Wages above this are outliers.
$143.9K - $153.7K
38% of jobs
$153.7K - $163.5K
0% of jobs
$163.5K - $173.3K
1% of jobs
$173.3K - $183.2K
1% of jobs
$183.2K - $193K
1% of jobs
$85.1K
$147.4K
$193K
How much do rtl design jobs pay per year?
As of Jul 26, 2026, the average yearly pay for rtl design in Oregon is $147,352.00, according to ZipRecruiter salary data. Most workers in this role earn between $143,800.00 and $143,800.00 per year, depending on experience, location, and employer.
What are the key skills and qualifications needed to thrive in the Rtl Design position, and why are they important?
To thrive as an RTL Design engineer, you need a solid background in digital logic design, computer architecture, and proficiency in hardware description languages such as Verilog or VHDL, typically supported by a degree in electrical or computer engineering. Familiarity with EDA tools like Synopsys, Cadence, or Mentor Graphics, and experience with FPGA/ASIC flows, are highly valuable, as are relevant industry certifications. Strong problem-solving skills, attention to detail, and effective communication foster successful collaboration with verification and physical design teams. These skills are crucial for delivering robust, efficient hardware solutions in complex chip development projects.
What does a typical day look like for an RTL Design engineer and how do they interact with other teams?
A typical day for an RTL Design engineer involves writing and optimizing RTL code, running simulations, debugging designs, and reviewing results from verification teams. Collaboration is key, as you will frequently interact with verification engineers, physical design teams, and architects to ensure the design meets both functional and performance requirements. You may also participate in design reviews, resolve issues found during testing, and work with project managers to meet deadlines. This cross-functional teamwork creates a dynamic environment where communication and problem-solving skills are highly valued, helping ensure the successful delivery of silicon products.
What does an RTL designer do?
An RTL (Register Transfer Level) designer creates digital circuit designs using hardware description languages like VHDL or Verilog. They develop and verify the logic for integrated circuits, working closely with verification engineers and using simulation tools to ensure correct functionality before manufacturing.
What is the salary of RTL designer?
The salary of an RTL (Register Transfer Level) designer typically ranges from $70,000 to $130,000 annually, depending on experience, location, and industry. Entry-level positions may start lower, while experienced engineers with skills in VHDL or Verilog can earn higher salaries, especially in high-demand tech hubs.
How do I get into RTL design?
To get into RTL design, you should have a strong understanding of digital logic design, hardware description languages like VHDL or Verilog, and experience with FPGA or ASIC development tools. A bachelor's degree in electrical engineering, computer engineering, or a related field is typically required, and gaining hands-on experience through internships or personal projects can be highly beneficial.
What is an RTL Design job?
An RTL (Register Transfer Level) Design job involves designing and implementing digital circuits using hardware description languages (HDLs) like Verilog or VHDL. RTL engineers translate high-level specifications into synthesizable logic, ensuring functionality, power efficiency, and performance. They collaborate with verification engineers to test and debug designs before fabrication. This role is crucial in developing ASICs, FPGAs, and other digital hardware components.
Is RTL design a good career?
RTL (Register Transfer Level) design is a specialized field within digital design and hardware engineering, focusing on creating and optimizing digital circuits using hardware description languages like VHDL or Verilog. It offers opportunities in semiconductor, electronics, and chip design industries, often requiring knowledge of digital logic, verification tools, and hardware development processes. The career can be stable and well-paying for those with technical skills and industry experience.
What are the most commonly searched types of Rtl Design jobs in Oregon? The most popular types of Rtl Design jobs in Oregon are:
What are popular job titles related to Rtl Design jobs in Oregon? For Rtl Design jobs in Oregon, the most frequently searched job titles are:
What job categories do people searching Rtl Design jobs in Oregon look for? The top searched job categories for Rtl Design jobs in Oregon are:
What cities in Oregon are hiring for Rtl Design jobs? Cities in Oregon with the most Rtl Design job openings:
Apple rating
8.0
Based on 675 frontline employees who took The Breakroom Quiz
7th of 30 rated technology retailers
Job description
At Apple, we work every day to craft products that enrich people's lives. If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. This is an exciting position in the world class Apple mixed-signal silicon design team!
This role will build upon your solid foundation in digital logic circuits while introducing mixed-signal and analog circuit design and features. You will work with a variety of flows fundamental to modern silicon engineering: modeling and integrating high-performance mixed-signal and analog IPs into high-speed digital circuits, ensuring formal equivalence between custom designs and their abstract representations. This is an excellent opportunity to gain valuable experience in software methods and analysis, which are increasingly crucial across the semiconductor industry.
As a member of our dynamic team, you will have the exceptional opportunity to help create the next generation of products that will delight and inspire millions of Apple customers every day. You will work to specify, design, verify, and support lab bring-up of sophisticated digital and mixed-signal circuits with signal processing capabilities.
Description
In this role, you will be responsible for specifying and/or micro-architecting digital and signal processing blocks in sophisticated mixed-signal circuits. You will be responsible for RTL coding of blocks specified by you or others, including implementation of DSP algorithms. You will also participate in the design verification and bring-up of such blocks by writing meaningful assertions, debugging code, and otherwise interacting with the design verification team. You will contribute to the lab bring-up of those circuits by potentially writing test scripts, analyzing lab data, proposing experiments, and validating signal processing performance.","responsibilities":"RTL Design & Implementation: Develop and optimize RTL code in Verilog/SystemVerilog for mixed-signal digital blocks and signal processing pipelines
DSP Algorithm Translation: Collaborate with algorithm engineers to translate DSP concepts (filtering, transforms, modulation, signal analysis) into efficient, high-performance RTL implementations
Design Verification: Write comprehensive assertions, unit-level testbenches, and participate in functional verification using industry-standard methodologies
Integration & Bring-up: Partner with cross-functional teams to integrate complex IPs, validate performance in silicon, and support lab characterization
Collaborative Problem-Solving: Work effectively with analog designers, algorithm engineers, verification specialists, and system architects across disciplinary boundaries
Preferred Qualifications
Front-end tools expertise (Verilog simulators, linters, clock-domain crossing checkers)
Synthesis, static timing analysis, and design-for-test (DFT)
SystemVerilog assertions, checkers, and advanced verification techniques
Scripting languages (Perl, Python)
Formal verification and low-power design methodologies
Hardware-software co-design and system-level optimization
Hands-on DSP experience: signal processing concepts, RTL algorithm implementation, hardware optimization techniques (pipelining, parallelization, resource sharing)
Intermediate to advanced GenAI proficiency: Using AI tools for SystemVerilog design, validation, optimization, and understanding GenAI capabilities/limitations in hardware design
Minimum Qualifications
Bachelors of Science in Electrical Engineering.
This role will build upon your solid foundation in digital logic circuits while introducing mixed-signal and analog circuit design and features. You will work with a variety of flows fundamental to modern silicon engineering: modeling and integrating high-performance mixed-signal and analog IPs into high-speed digital circuits, ensuring formal equivalence between custom designs and their abstract representations. This is an excellent opportunity to gain valuable experience in software methods and analysis, which are increasingly crucial across the semiconductor industry.
As a member of our dynamic team, you will have the exceptional opportunity to help create the next generation of products that will delight and inspire millions of Apple customers every day. You will work to specify, design, verify, and support lab bring-up of sophisticated digital and mixed-signal circuits with signal processing capabilities.
Description
In this role, you will be responsible for specifying and/or micro-architecting digital and signal processing blocks in sophisticated mixed-signal circuits. You will be responsible for RTL coding of blocks specified by you or others, including implementation of DSP algorithms. You will also participate in the design verification and bring-up of such blocks by writing meaningful assertions, debugging code, and otherwise interacting with the design verification team. You will contribute to the lab bring-up of those circuits by potentially writing test scripts, analyzing lab data, proposing experiments, and validating signal processing performance.","responsibilities":"RTL Design & Implementation: Develop and optimize RTL code in Verilog/SystemVerilog for mixed-signal digital blocks and signal processing pipelines
DSP Algorithm Translation: Collaborate with algorithm engineers to translate DSP concepts (filtering, transforms, modulation, signal analysis) into efficient, high-performance RTL implementations
Design Verification: Write comprehensive assertions, unit-level testbenches, and participate in functional verification using industry-standard methodologies
Integration & Bring-up: Partner with cross-functional teams to integrate complex IPs, validate performance in silicon, and support lab characterization
Collaborative Problem-Solving: Work effectively with analog designers, algorithm engineers, verification specialists, and system architects across disciplinary boundaries
Preferred Qualifications
Front-end tools expertise (Verilog simulators, linters, clock-domain crossing checkers)
Synthesis, static timing analysis, and design-for-test (DFT)
SystemVerilog assertions, checkers, and advanced verification techniques
Scripting languages (Perl, Python)
Formal verification and low-power design methodologies
Hardware-software co-design and system-level optimization
Hands-on DSP experience: signal processing concepts, RTL algorithm implementation, hardware optimization techniques (pipelining, parallelization, resource sharing)
Intermediate to advanced GenAI proficiency: Using AI tools for SystemVerilog design, validation, optimization, and understanding GenAI capabilities/limitations in hardware design
Minimum Qualifications
Bachelors of Science in Electrical Engineering.
About Apple
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Cupertino, CA, US
Year founded
1976