SoC Verification Engineer
$141K - $200K/yr
Position Overview As a SoC Design Verification Engineer, you will play a pivotal role in ensuring that Intel's complex System-on-Chip (SoC) designs meet functional specifications and deliver high ...
SoC Verification Engineer
$141K - $200K/yr
Position Overview As a SoC Design Verification Engineer, you will play a pivotal role in ensuring that Intel's complex System-on-Chip (SoC) designs meet functional specifications and deliver high ...
Design Verification Engineer
Beaverton, OR · On-site
$141K - $172K/yr
Design Verification Engineers at Apple are responsible for verifying the functionality and ... You own ensuring the quality of the SOC or an IP or subsystem. This requires you to review design ...
Design Verification Engineer
Beaverton, OR · On-site
$141K - $172K/yr
Design Verification Engineers at Apple are responsible for verifying the functionality and ... You own ensuring the quality of the SOC or an IP or subsystem. This requires you to review design ...
Design Verification Engineer
$141K - $172K/yr
Design Verification Engineers at Apple are responsible for verifying the functionality and ... You own ensuring the quality of the SOC or an IP or subsystem. This requires you to review design ...
Design Verification Engineer
$141K - $172K/yr
Design Verification Engineers at Apple are responsible for verifying the functionality and ... You own ensuring the quality of the SOC or an IP or subsystem. This requires you to review design ...
Design Verification Engineer
Beaverton, OR · On-site
$141K - $172K/yr
Design Verification Engineers at Apple are responsible for verifying the functionality and ... You own ensuring the quality of the SOC or an IP or subsystem. This requires you to review design ...
Design Verification Engineer
Beaverton, OR · On-site
$141K - $172K/yr
Design Verification Engineers at Apple are responsible for verifying the functionality and ... You own ensuring the quality of the SOC or an IP or subsystem. This requires you to review design ...
Design Verification Engineer
Beaverton, OR · On-site
$141K - $172K/yr
Design Verification Engineers at Apple are responsible for verifying the functionality and ... You own ensuring the quality of the SOC or an IP or subsystem. This requires you to review design ...
Design Verification Engineer
Beaverton, OR · On-site
$141K - $172K/yr
Design Verification Engineers at Apple are responsible for verifying the functionality and ... You own ensuring the quality of the SOC or an IP or subsystem. This requires you to review design ...
Design Verification Engineer
$141K - $172K/yr
Design Verification Engineers at Apple are responsible for verifying the functionality and ... You own ensuring the quality of the SOC or an IP or subsystem. This requires you to review design ...
Design Verification Engineer
$141K - $172K/yr
Design Verification Engineers at Apple are responsible for verifying the functionality and ... You own ensuring the quality of the SOC or an IP or subsystem. This requires you to review design ...
Design Verification Engineer
Beaverton, OR · On-site
$141K - $172K/yr
We have an opportunity for an outstandingly hardworking design verification engineer! As a member ... You will also learn to develop block, IP and SoC level test-benches track and report DV progress ...
Design Verification Engineer
Beaverton, OR · On-site
$141K - $172K/yr
We have an opportunity for an outstandingly hardworking design verification engineer! As a member ... You will also learn to develop block, IP and SoC level test-benches track and report DV progress ...
Design Verification Engineer
Beaverton, OR · On-site
$141K - $172K/yr
We have an opportunity for an outstandingly hardworking design verification engineer! As a member ... You will also learn to develop block, IP and SoC level test-benches track and report DV progress ...
Design Verification Engineer
Beaverton, OR · On-site
$141K - $172K/yr
We have an opportunity for an outstandingly hardworking design verification engineer! As a member ... You will also learn to develop block, IP and SoC level test-benches track and report DV progress ...
Design Verification Engineer
$141K - $172K/yr
We have an opportunity for an outstandingly hardworking design verification engineer! As a member ... You will also learn to develop block, IP and SoC level test-benches track and report DV progress ...
Design Verification Engineer
$141K - $172K/yr
We have an opportunity for an outstandingly hardworking design verification engineer! As a member ... You will also learn to develop block, IP and SoC level test-benches track and report DV progress ...
Design Verification Engineer
$141K - $172K/yr
We have an opportunity for an outstandingly hardworking design verification engineer! As a member ... You will also learn to develop block, IP and SoC level test-benches track and report DV progress ...
Design Verification Engineer
$141K - $172K/yr
We have an opportunity for an outstandingly hardworking design verification engineer! As a member ... You will also learn to develop block, IP and SoC level test-benches track and report DV progress ...
Design Verification Engineer
$184K - $324K/yr
Design Verification Engineers at Apple are responsible for verifying the functionality and ... You own ensuring the quality of the SOC or an IP or subsystem. This requires you to review design ...
Design Verification Engineer
$184K - $324K/yr
Design Verification Engineers at Apple are responsible for verifying the functionality and ... You own ensuring the quality of the SOC or an IP or subsystem. This requires you to review design ...
Design Verification Engineer
Beaverton, OR · On-site
$141K - $172K/yr
Design Verification Engineers at Apple are responsible for verifying the functionality and ... You own ensuring the quality of the SOC or an IP or subsystem. This requires you to review design ...
Design Verification Engineer
Beaverton, OR · On-site
$141K - $172K/yr
Design Verification Engineers at Apple are responsible for verifying the functionality and ... You own ensuring the quality of the SOC or an IP or subsystem. This requires you to review design ...
Design Verification Engineer
$184K - $324K/yr
Design Verification Engineers at Apple are responsible for verifying the functionality and ... You own ensuring the quality of the SOC or an IP or subsystem. This requires you to review design ...
Design Verification Engineer
$184K - $324K/yr
Design Verification Engineers at Apple are responsible for verifying the functionality and ... You own ensuring the quality of the SOC or an IP or subsystem. This requires you to review design ...
Design Verification Engineer
$184K - $324K/yr
Design Verification Engineers at Apple are responsible for verifying the functionality and ... You own ensuring the quality of the SOC or an IP or subsystem. This requires you to review design ...
Design Verification Engineer
$184K - $324K/yr
Design Verification Engineers at Apple are responsible for verifying the functionality and ... You own ensuring the quality of the SOC or an IP or subsystem. This requires you to review design ...
Design Verification Engineer
$141K - $172K/yr
Design Verification Engineers at Apple are responsible for verifying the functionality and ... You own ensuring the quality of the SOC or an IP or subsystem. This requires you to review design ...
Design Verification Engineer
$141K - $172K/yr
Design Verification Engineers at Apple are responsible for verifying the functionality and ... You own ensuring the quality of the SOC or an IP or subsystem. This requires you to review design ...
OR · On-site
$130K - $200K/yr
The Role We are seeking an ASIC Design Verification Engineer whose role will be to verify the ... ASIC/SoC verification. * Solid understanding of SystemVerilog, digital logic, and hardware ...
Director, SoC Design Engineering
$148K - $180K/yr
The Role and Impact We are seeking a highly experienced a Director, SoC Design Engineering, to lead the functional verification efforts for cutting-edge system-on-chip (SoC) designs. In this ...
Director, SoC Design Engineering
$148K - $180K/yr
The Role and Impact We are seeking a highly experienced a Director, SoC Design Engineering, to lead the functional verification efforts for cutting-edge system-on-chip (SoC) designs. In this ...
SoC Physical Design Verification Engineer
Beaverton, OR · On-site
$141K - $145K/yr
... verification of an SOC. Description • As a member of our physical design team, you will perform ... engineering efforts. • You will work on padring, bump, RDL design, and working with the package ...
SoC Physical Design Verification Engineer
Beaverton, OR · On-site
$141K - $145K/yr
... verification of an SOC. Description • As a member of our physical design team, you will perform ... engineering efforts. • You will work on padring, bump, RDL design, and working with the package ...
SoC Physical Design Verification Engineer
$129K - $194K/yr
... verification of an SOC. Description • As a member of our physical design team, you will perform ... engineering efforts. • You will work on padring, bump, RDL design, and working with the package ...
SoC Physical Design Verification Engineer
$129K - $194K/yr
... verification of an SOC. Description • As a member of our physical design team, you will perform ... engineering efforts. • You will work on padring, bump, RDL design, and working with the package ...
SoC Physical Design Verification Engineer
$129K - $194K/yr
... verification of an SOC. Description • As a member of our physical design team, you will perform ... engineering efforts. • You will work on padring, bump, RDL design, and working with the package ...
SoC Physical Design Verification Engineer
$129K - $194K/yr
... verification of an SOC. Description • As a member of our physical design team, you will perform ... engineering efforts. • You will work on padring, bump, RDL design, and working with the package ...
Soc Design Verification Engineer information
What are some common challenges faced by SoC Design Verification Engineers during the verification process?
SoC Design Verification Engineers often encounter challenges related to the increasing complexity of modern system-on-chip architectures, such as integrating numerous IP blocks and ensuring robust communication between them. Debugging failures in large-scale simulations and managing tight project deadlines can also be demanding. Additionally, adapting to evolving verification methodologies and tools, as well as collaborating effectively with design and firmware teams to resolve issues quickly, are common aspects of the role. Successful engineers leverage strong problem-solving skills and proactive communication to navigate these challenges.
What are the key skills and qualifications needed to thrive as a SoC Design Verification Engineer, and why are they important?
To thrive as an SoC Design Verification Engineer, you need a solid background in digital design, computer architecture, and verification methodologies, typically supported by a degree in electrical or computer engineering. Familiarity with hardware description languages (HDL) like Verilog or VHDL, verification tools such as UVM/SystemVerilog, and simulation/debugging environments is essential. Strong analytical thinking, problem-solving abilities, and effective communication skills help in collaborating with design teams and troubleshooting complex issues. These skills and qualities are vital to ensure the reliability, functionality, and timely delivery of complex system-on-chip products.
What are SoC Design Verification Engineers?
SoC (System-on-Chip) Design Verification Engineers are professionals who ensure that integrated circuits, which combine multiple components onto a single chip, function correctly according to their specifications. They use various verification methodologies and tools to simulate, test, and debug the design before it is manufactured. Their work involves creating testbenches, running simulation tests, and collaborating with design engineers to identify and resolve issues early in the development cycle. This helps prevent costly errors and ensures the final product meets quality and performance standards.
What is the difference between Soc Design Verification Engineer vs Soc Validation Engineer?
| Aspect | Soc Design Verification Engineer | Soc Validation Engineer |
|---|---|---|
| Primary Focus | Verifying design correctness through simulation and testing during development | Validating the final product to ensure it meets specifications and functions in real-world scenarios |
| Work Environment | Design teams, simulation labs, hardware testing | Product testing, field testing, customer environments |
| Required Credentials | Bachelor's or master's in Electrical Engineering, VLSI, or related fields; knowledge of verification tools | Bachelor's or master's in Electrical Engineering, VLSI, or related fields; experience with testing methodologies |
The Soc Design Verification Engineer primarily focuses on verifying the design correctness during development, while the Soc Validation Engineer tests the final product to ensure it functions correctly in real-world conditions. Both roles require similar educational backgrounds and industry experience, but their responsibilities differ in the development lifecycle.
What are popular job titles related to Soc Design Verification Engineer jobs in Oregon? For Soc Design Verification Engineer jobs in Oregon, the most frequently searched job titles are:
What job categories do people searching Soc Design Verification Engineer jobs in Oregon look for? The top searched job categories for Soc Design Verification Engineer jobs in Oregon are:
$141K - $200K/yr
Full-time
Medical, Retirement, PTO
Posted 6 days ago
Intel rating
8.7
Based on 147 frontline employees who took The Breakroom Quiz
19th of 156 rated electronics manufacturers
Job description
Job Details:Job Description: About the Team
You will be joining Intel's cutting-edge product development group, a team focused on designing and verifying advanced semiconductor solutions. This group is at the forefront of innovation, delivering high-quality, scalable products that drive Intel's leadership in technology and performance. By contributing your skills here, you will help shape the future of computing and enable groundbreaking advancements in the industry.
Position OverviewAs a SoC Design Verification Engineer, you will play a pivotal role in ensuring that Intel's complex System-on-Chip (SoC) designs meet functional specifications and deliver high-quality performance. You will design scalable and reusable verification plans, develop test environments, and execute tests to uncover issues and improve functionality. Your contributions will directly enhance Intel's product quality and ensure optimal performance in presilicon development.
Key Responsibilities- Create and update UVM-based test bench generation and test case creation
- Define and develop scalable and reusable block, subsystem, and SoC verification plans
- Create test benches and verification environments that align with microarchitecture specifications
- Execute verification plans, including emulation and system simulation models, to ensure design functionality and uncover bugs
- Debug and root cause issues in presilicon environments, implementing corrective measures to address failures
- Collaborate with architects, RTL developers, postsilicon teams, and physical design teams to improve verification of complex architectural features
- Document and maintain test plans, driving technical reviews with design and architecture teams
- Integrate security coverage activities within test plans, including regression and debug tests
- Maintain and improve existing functional verification infrastructure and methodologies
- Absorb learnings from postsilicon development and incorporate feedback into improved verification strategies
- Ability to work collaboratively across interdisciplinary teams
- Strong communication skills with the ability to work across interdisciplinary teams
- Passion for tackling complex problems and delivering innovative solutions
Minimum Qualifications
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, with 4+ years of hands-on experience in SoC design verification, including demonstrated expertise in OVM/UVM methodologies, debugging, and test planningOR
- Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, with 3+ years of hands-on experience in SoC design verification, including demonstrated expertise in OVM/UVM methodologies, debugging, and test planning
The experience must include:
- AMBA protocols such as CHI, AXI, AHB, and APB with industry-standard VIP from various EDA vendors
- Creation and updating of UVM-based test benches and test case creation
Preferred Qualifications
- Experience with postsilicon validation and incorporating feedback into presilicon test plans
- Familiarity with emulation models and system simulation tools for performance analysis
We invite you to bring your expertise and creativity to Intel, where your contributions will make a lasting impact on future technology. Join us and shape the future of computing with your skills and dedication.
Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, Texas, AustinAdditional Locations:US, California, Santa Clara, US, Oregon, HillsboroPosting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefitsWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $141,910.00-200,340.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
About Intel
Sourced by ZipRecruiter
Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth
Industry
Manufacturing
Company size
10,000+ Employees
Headquarters location
Santa Clara, CA, US
Year founded
1968