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Senior Asic Design Engineer Jobs in Oregon (NOW HIRING)

ServerLogic

Senior ASIC Design Engineer

Beaverton, OR · On-site

Sr/ ASIC Design Engineer (5+ Years of Experience) DESCRIPTION OF POSITION/DUTIES - * Architect a block of an ASIC and write a microarchitecture specification (MAS) for the block * Collaborate with ...

Nvidia

Senior ASIC Design Engineer - GPU

Hillsboro, OR · Hybrid

We are now looking for a Senior ASIC Engineer! NVIDIA is searching for an outstanding ASIC Engineer ... As a Senior Design Engineer at NVIDIA, you will be responsible for the development and micro ...

K2 Space

OR · On-site

$170K - $250K/yr

The Role We are seeking a Senior ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the ...

K2 Space

OR · On-site

$170K - $250K/yr

The Role We are seeking a Senior ASIC Physical Design Engineer to help implement advanced SoCs that power next-generation satellite and space systems. In this role, you will contribute to the full ...

Apple

ASIC Design Engineer

Beaverton, OR · On-site

Description As an ASIC Design Engineer, your responsibilities span various aspects of SOC design: - Write microarchitecture and/or design specifications - Design, implement, and debug complex logic ...

Apple

ASIC Design Engineer

Beaverton, OR

Description As an ASIC Design Engineer, your responsibilities span various aspects of SOC design: - Write microarchitecture and/or design specifications - Design, implement, and debug complex logic ...

Apple

ASIC Design and Integration Engineer

Beaverton, OR

$150K - $277K/yr

Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer to join our dynamic group. In this role, you will develop custom SoCs that drive the performance ...

Apple

ASIC Design and Integration Engineer

Beaverton, OR

$150K - $277K/yr

Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer to join our dynamic group. In this role, you will develop custom SoCs that drive the performance ...

Apple

ASIC Design and Integration Engineer

Beaverton, OR

$184K - $324K/yr

Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer to join our dynamic group. In this role, you will develop custom SoCs that drive the performance ...

Apple

ASIC Design and Integration Engineer

Beaverton, OR

$184K - $324K/yr

Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer to join our dynamic group. In this role, you will develop custom SoCs that drive the performance ...

Apple Inc.

ASIC Design Engineer

Beaverton, OR · On-site

$150 - $210/hr

Description As an ASIC Design Engineer, your responsibilities span various aspects of SOC design: * Write microarchitecture and/or design specifications * Design, implement, and debug complex logic ...

K2 Space

OR · On-site

$170K - $250K/yr

The Role We are seeking a Senior ASIC Emulation Engineer who will lead the bring-up, deployment ... You will work closely with architecture, RTL design, DFT, DV, firmware, physical design, and ...

Nvidia

OR · Hybrid

The NVIDIA Clocks Team is looking for an excellent Senior ASIC Verification engineer with extensive ... The complexity of the clocks and resets design has increased many folds. This requires ...

K2 Space

OR · On-site

$190K - $285K/yr

The Role We are seeking a Principal ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define ...

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Senior Asic Design Engineer information

See Oregon salary details

$148K

$187.8K

$232.1K

How much do senior asic design engineer jobs pay per year?

As of Aug 10, 2026, the average yearly pay for senior asic design engineer in Oregon is $187,830.00, according to ZipRecruiter salary data. Most workers in this role earn between $168,100.00 and $206,200.00 per year, depending on experience, location, and employer.

What does a senior ASIC design engineer do?

A Senior ASIC Design Engineer is responsible for designing and developing Application-Specific Integrated Circuits (ASICs) used in a wide range of electronic devices. They lead the architecture, implementation, and verification of complex digital or mixed-signal circuits, often collaborating with cross-functional teams. This senior role involves optimizing designs for performance, power, and area while ensuring that the final product meets stringent technical and quality requirements. Additionally, they may mentor junior engineers and contribute to design methodologies and best practices within the organization.

What are the key skills and qualifications needed to thrive as a senior ASIC design engineer?

To thrive as a Senior ASIC Design Engineer, you need deep expertise in digital and/or analog circuit design, strong knowledge of hardware description languages (HDLs) like Verilog or VHDL, and a relevant engineering degree. Familiarity with EDA tools such as Synopsys, Cadence, and Mentor Graphics, as well as experience with simulation, synthesis, and verification methodologies, is typically required. Outstanding problem-solving, collaboration, and communication skills set top performers apart in this role. These competencies ensure efficient design cycles, robust chip functionality, and successful delivery of complex semiconductor projects.

What is the difference between Senior Asic Design Engineer vs Digital IC Design Engineer?

AspectSenior Asic Design EngineerDigital IC Design Engineer
Required CredentialsBachelor's/Master's in Electrical Engineering, VLSI, or related fields; experience in ASIC designBachelor's/Master's in Electrical Engineering, VLSI, or related fields; focus on digital circuit design
Work EnvironmentDesign teams in semiconductor or tech companies, hardware development labsIntegrated circuit design teams, research labs, semiconductor companies
Employer & Industry UsageUsed in ASIC development, FPGA design, hardware accelerationUsed in digital chip design, FPGA development, digital system integration

The main difference is that a Senior Asic Design Engineer specializes in designing application-specific integrated circuits, often leading complex projects, while a Digital IC Design Engineer focuses on digital circuit design within integrated circuits. Both roles require similar educational backgrounds and work environments but differ in project scope and specialization.

What are some common challenges senior ASIC design engineers face when collaborating with cross-functional teams?

Senior ASIC Design Engineers often work closely with verification, software, and systems teams throughout the development cycle. One common challenge is ensuring clear communication of design specifications and changes, as misunderstandings can lead to integration issues or delays. Balancing multiple project timelines and adapting to evolving requirements from other departments can also be demanding. Building strong, collaborative relationships and using robust documentation and project management tools are key to overcoming these challenges.
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Senior Asic Design Engineer jobs near you
Infographic showing various Senior Asic Design Engineer job openings in Oregon as of August 2026, with employment types broken down into 1% Internship, 84% Full Time, 9% Part Time, 5% Contract, and 1% Nights. Highlights an 84% Physical, 5% Hybrid, and 11% Remote job distribution, with an average salary of $187,830 per year, or $90.3 per hour.

Senior ASIC Design Engineer

ServerLogic

Beaverton, OR • On-site

Full-time

Re-posted 12 days ago

Job description

Sr/ ASIC Design Engineer
(5+ Years of Experience)
DESCRIPTION OF POSITION/DUTIES -
  1. Architect a block of an ASIC and write a microarchitecture specification (MAS) for the block
  2. Collaborate with other team members to integrate the block with the full chip
  3. Use Verilog to design and System Verilog for block level verification
  4. Assist the Verification team in reviewing and debugging test cases
  5. Run LINT and CDC checks on the RTL code and fix accordingly.
  6. Assist with synthesis and FPGA emulation.

QUALIFICATIONS -
  1. BA/MS degree and 5+ years of relevant work experience.
  2. Demonstrate knowledge of Verilog for chip design and verification.
  3. Must understand the ASIC flow from MAS to silicon including RTL design, verification, synthesis, timing constraints, GLS, FPGA prototyping, and first silicon bring up and debug.
  4. Understanding of digital design and verification practices.
  5. Be able to take a specification, write RTL and simulation vectors to verify their RTL.
  6. One prior RTL design is a requirement.
  7. Experience with USB 2.0, USB 3.2, USB4, or PCIe is desired.

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