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Tapeout Design Engineer Jobs in Oregon (NOW HIRING)

Intel

Silicon Packaging Design Engineer

Hillsboro, OR · On-site

$148K/yr

Drive end-to-end development of test board designs from concept through tapeout. * Perform board ... Partner closely with package design, test engineering, and validation teams to define board ...

Apple

SoC Physical Design Engineer, STA/Timing

Beaverton, OR · On-site

$141K - $145K/yr

... tapeout) for a highly complex SOC using state of the art process technology. Description - Work ... large design STA and/or Timing Closure. Programming skills with Perl and TCL. Preferred ...

Apple

SoC Physical Design Engineer, STA/Timing

Beaverton, OR · On-site

$141K - $145K/yr

... tapeout) for a highly complex SOC using state of the art process technology. Description - Work ... programming skills with TCL Preferred Qualifications Experience with large design STA and/or Timing ...

Apple

SoC Physical Design Engineer, STA/Timing

Beaverton, OR · On-site

$141K - $145K/yr

... tapeout) for a highly complex SoC using state of the art process technology. Description - Work ... Good programming skills with Perl and TCL. Experience with large design STA and Timing Closure.

K2 Space

Senior ASIC Physical Design Engineer

OR · On-site +1

$170K - $250K/yr

... tapeout preparation. * Contribute to methodology development, tool evaluation, and flow ... Computer Engineering, or related field. * 5-10 years of experience in ASIC physical design for ...

Apple

SoC Physical Design Engineer, PnR

Beaverton, OR · On-site

$141K - $145K/yr

In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC utilizing innovative process ...

Apple

SoC Physical Design Verification Engineer

Beaverton, OR · On-site

$141K - $145K/yr

We work directly with the implementation team during the entire chip design cycle to drive signoff closure for tapeout. • You will lead schedules and support cross-functional engineering efforts ...

Apple

SoC Physical Design Engineer, PnR

Beaverton, OR · On-site

$141K - $145K/yr

In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC utilizing innovative process ...

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All JobsTapeout Design Engineer JobsTapeout Design Engineer Jobs in Oregon

Tapeout Design Engineer information

What is a tapeout design engineer?

Tapeout Design Engineers are professionals responsible for finalizing the layout and design of integrated circuits (ICs) before manufacturing. They ensure that all design specifications are met, and that the chip layout is error-free and ready for fabrication. Their work involves collaborating with design, verification, and foundry teams to deliver a manufacturable design, often using tools for physical verification, design rule checking, and layout-versus-schematic checks. This role is critical in the semiconductor industry, as any errors at tapeout can result in costly manufacturing delays. Tapeout Design Engineers play a key role in bringing new microchips from concept to production.

What are the key skills and qualifications needed to thrive as a tapeout design engineer?

To thrive as a Tapeout Design Engineer, you need a solid background in semiconductor physics, digital/analog circuit design, and a relevant engineering degree. Proficiency with EDA tools such as Cadence, Synopsys, and experience with physical verification, DRC/LVS checks, and scripting languages like Python or TCL are typically required. Strong attention to detail, problem-solving skills, and effective communication are valuable soft skills in this role. These skills and qualities are crucial for ensuring error-free silicon fabrication, efficient workflow, and successful collaboration across engineering teams.

What are some common challenges tapeout design engineers face during the tapeout process, and how can they be addressed?

Tapeout Design Engineers often encounter tight deadlines, last-minute design changes, and the need to coordinate between multiple teams such as layout, verification, and fabrication. Addressing these challenges typically involves proactive communication, thorough planning, and the use of automated verification tools to catch errors early. Effective collaboration and robust documentation help ensure that any issues are quickly identified and resolved, minimizing the risk of costly delays or rework in the fabrication stage.

What is the difference between Tapeout Design Engineer vs ASIC Design Engineer?

AspectTapeout Design EngineerASIC Design Engineer
CredentialsBachelor's or Master's in Electrical Engineering or related field; knowledge of EDA toolsBachelor's or Master's in Electrical Engineering or related field; strong digital design skills
Work EnvironmentSemiconductor companies, chip design firms, EDA tool providersSemiconductor companies, integrated circuit design firms
Industry UsageFocuses on final chip layout and manufacturing readinessDesigns the digital architecture and logic of chips

While both roles require a background in electrical engineering and familiarity with EDA tools, a Tapeout Design Engineer specializes in preparing the final chip layout for manufacturing, ensuring design rules are met. An ASIC Design Engineer focuses on creating the digital logic and architecture of integrated circuits. The roles often collaborate but differ mainly in their stage of the design process and specific responsibilities.

What are popular job titles related to Tapeout Design Engineer jobs in Oregon?

For Tapeout Design Engineer jobs in Oregon, the most frequently searched job titles are:

What job categories do people searching Tapeout Design Engineer jobs in Oregon look for?

The top searched job categories for Tapeout Design Engineer jobs in Oregon are:

Tapeout Design Engineer jobs near you
Infographic showing various Tapeout Design Engineer job openings in Oregon as of August 2026, with employment types broken down into 85% Full Time, 12% Part Time, and 3% Contract. Highlights an 81% Physical, 5% Hybrid, and 14% Remote job distribution.

Silicon Packaging Design Engineer

Intel

Hillsboro, OR • On-site

$148K/yr

Full-time

Medical, Retirement, PTO

Re-posted 5 hours ago

Intel rating

8.7

Company rating: 8.7 out of 10

Based on 147 frontline employees who took The Breakroom Quiz

18th of 159 rated electronics manufacturers

Job description

Job Details:Job Description: 

We are seeking an experienced Silicon Packaging Design Engineer with a strong background in board design and package-board integration to drive the end-to-end development of test boards supporting advanced silicon package validation and characterization. The successful candidate will be responsible for board design execution from concept through tapeout, ensuring high-quality, manufacturable designs that meet electrical, mechanical, performance, and cost objectives.

This role requires close collaboration with package design, test vehicle design, validation, and laboratory teams to optimize board requirements, package-board performance, and system-level integration. The ideal candidate will bring deep technical expertise in PCB design, signal integrity considerations, manufacturing requirements, and design rule compliance, along with a proven track record of delivering complex designs in high-volume semiconductor environments.

Key Responsibilities

  • Drive end-to-end development of test board designs from concept through tapeout.
  • Perform board planning, floor planning, routing studies, and physical layout implementation.
  • Conduct board fit and routing studies to evaluate design, performance, manufacturability, and cost tradeoffs.
  • Partner closely with package design, test engineering, and validation teams to define board requirements and optimize package-board interactions.
  • Develop and validate board connectivity, ensuring design integrity and compliance with project specifications.
  • Perform design rule checks (DRCs) and manufacturing design rule validation to ensure successful fabrication and assembly.
  • Lead internal and external design reviews and drive resolution of design issues and DRC violations.
  • Collaborate with board fabrication and assembly vendors to obtain design approval and support manufacturing readiness.
  • Define and maintain board design guidelines, standards, and best practices.
  • Analyze design data and technical results to identify opportunities for optimization and continuous improvement.
  • Create and maintain design documentation and release collateral within Product Lifecycle Management (PLM) systems.
  • Support root cause analysis and troubleshooting activities related to board design, package-board integration, and test hardware performance.

What You'll Bring

  • Strong technical leadership and ownership mindset.
  • Complex projects independently while collaborating across global teams.
  • Excellent analytical and troubleshooting skills.
  • Customer-focused and results-driven approach.
  • Passion for innovation and continuous improvement in silicon packaging and board design.
Qualifications:

Minimum qualifications are required to be initially considered for this position.

Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. This position is not eligible for Intel immigration sponsorship

Minimum Qualifications

  • Master's degree in Electrical Engineering or Mechanical Engineering.
  • +10 years of experience with PCB layout utilizing Cadence Allegro and Cadence Constraint Manager.
  • +5 years of experience in:
    • Hardware development including: Schematic Entry, Signal Integrity, and Power Delivery practices and theories, constraint entry, library creation, DFM, DFX.
    • Managing highly complex PCB designs both individually as well as part of a team while working across multiple sites.
    • Expertise in board design and development, interconnect methodologies, and manufacturability principles.
    • Expertise in various board technologies and manufacturing process and fundamentals.
    • Demonstrated experience and proficiency with board design rules and design rule check resolution.

Preferred Qualifications

  • Experience with additional PCB design tools such as Siemens Xpedition.
  • Minimum of 8 years of experience with a broad range of PCB form factors, HDI/Type4 PCB technology.
  • Previous experience with communicating with board manufacturing vendors to review and obtain design approval meeting vendors manufacturing capabilities.
  • Experience interacting with board vendors regarding their capability and design rules roadmap and align internal design teams on design rules roadmap.
  • Previous experience managing external CAD contract workers to meet project demands.
  • Manage multiple projects, schedules, and multi-disciplined teams in a dynamic, fast-paced environment working across organization boundaries and geographies.
Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, Arizona, PhoenixAdditional Locations:US, Oregon, HillsboroPosting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $164,470.00-232,190.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

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About Intel

Sourced by ZipRecruiter

Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth

Industry

Manufacturing

Company size

10,000+ Employees

Headquarters location

Santa Clara, CA, US

Year founded

1968

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