Senior ASIC Design Engineer
Beaverton, OR · On-site
Use Verilog to design and System Verilog for block level verification * Assist the Verification team in reviewing and debugging test cases * Run LINT and CDC checks on the RTL code and fix ...
Senior ASIC Design Engineer
Beaverton, OR · On-site
Use Verilog to design and System Verilog for block level verification * Assist the Verification team in reviewing and debugging test cases * Run LINT and CDC checks on the RTL code and fix ...
Emulation Verification Engineer
Beaverton, OR · On-site
$141K - $172K/yr
... Verilog/UVM - Develop random stimulus infrastructure by reusing existing UVM simulation constraints Minimum Qualifications Minimum of BS + 3 years relevant industry experience. Preferred ...
Emulation Verification Engineer
Beaverton, OR · On-site
$141K - $172K/yr
... Verilog/UVM - Develop random stimulus infrastructure by reusing existing UVM simulation constraints Minimum Qualifications Minimum of BS + 3 years relevant industry experience. Preferred ...
Emulation Verification Engineer
$141K - $172K/yr
... Verilog/System Verilog/UVM - Develop random stimulus infrastructure by reusing existing UVM simulation constraints Preferred Qualifications Understanding of the tool flow from RTL to Emulation is a ...
Emulation Verification Engineer
$141K - $172K/yr
... Verilog/System Verilog/UVM - Develop random stimulus infrastructure by reusing existing UVM simulation constraints Preferred Qualifications Understanding of the tool flow from RTL to Emulation is a ...
Emulation Verification Engineer
$141K - $172K/yr
... Verilog/System Verilog/UVM - Develop random stimulus infrastructure by reusing existing UVM simulation constraints Preferred Qualifications Understanding of the tool flow from RTL to Emulation is a ...
Emulation Verification Engineer
$141K - $172K/yr
... Verilog/System Verilog/UVM - Develop random stimulus infrastructure by reusing existing UVM simulation constraints Preferred Qualifications Understanding of the tool flow from RTL to Emulation is a ...
Emulation Verification Engineer
Beaverton, OR · On-site
$143K - $175K/yr
... Verilog/UVM - Develop random stimulus infrastructure by reusing existing UVM simulation constraints Minimum Qualifications Minimum of BS + 10 years relevant industry experience. Preferred ...
Emulation Verification Engineer
Beaverton, OR · On-site
$143K - $175K/yr
... Verilog/UVM - Develop random stimulus infrastructure by reusing existing UVM simulation constraints Minimum Qualifications Minimum of BS + 10 years relevant industry experience. Preferred ...
Emulation Verification Engineer
Beaverton, OR · On-site
$141K - $172K/yr
... Verilog/UVM - Develop random stimulus infrastructure by reusing existing UVM simulation constraints Minimum Qualifications Minimum of BS + 10 years relevant industry experience. Preferred ...
Emulation Verification Engineer
Beaverton, OR · On-site
$141K - $172K/yr
... Verilog/UVM - Develop random stimulus infrastructure by reusing existing UVM simulation constraints Minimum Qualifications Minimum of BS + 10 years relevant industry experience. Preferred ...
SoC Design and Verification
Hillsboro, OR · On-site
$148K - $180K/yr
Creating System Verilog / OVM test benches at the IP & SOC level and validating. * At least 1-year experience in any of the Scripting: Perl, Tcl, python. * Experience with low power design. * Must ...
SoC Design and Verification
Hillsboro, OR · On-site
$148K - $180K/yr
Creating System Verilog / OVM test benches at the IP & SOC level and validating. * At least 1-year experience in any of the Scripting: Perl, Tcl, python. * Experience with low power design. * Must ...
SoC Design and Verification
Hillsboro, OR · On-site
$148K - $180K/yr
Creating System Verilog / OVM test benches at the IP & SOC level and validating * At least 1 year experience in any of the Scripting: Perl, Tcl, python * Experience with low power design * Must have ...
SoC Design and Verification
Hillsboro, OR · On-site
$148K - $180K/yr
Creating System Verilog / OVM test benches at the IP & SOC level and validating * At least 1 year experience in any of the Scripting: Perl, Tcl, python * Experience with low power design * Must have ...
Senior Engineer, Digital Design Engineering
Beaverton, OR · On-site
$121K - $174K/yr
Medical
Dental
Vision
Retirement
PTO
Perform new digital design using Verilog RTL, Standard cells, and similar approaches as necessary for both mixed signal ASIC and FPGA designs. Document design work, present results, and participate ...
Senior Engineer, Digital Design Engineering
Beaverton, OR · On-site
$121K - $174K/yr
Medical
Dental
Vision
Retirement
PTO
Perform new digital design using Verilog RTL, Standard cells, and similar approaches as necessary for both mixed signal ASIC and FPGA designs. Document design work, present results, and participate ...
Senior Engineer, Digital Design Engineering
Beaverton, OR · On-site
$121K - $174K/yr
Medical
Dental
Vision
Retirement
PTO
Perform new digital design using Verilog RTL, Standard cells, and similar approaches as necessary for both mixed signal ASIC and FPGA designs. Document design work, present results, and participate ...
Senior Engineer, Digital Design Engineering
Beaverton, OR · On-site
$121K - $174K/yr
Medical
Dental
Vision
Retirement
PTO
Perform new digital design using Verilog RTL, Standard cells, and similar approaches as necessary for both mixed signal ASIC and FPGA designs. Document design work, present results, and participate ...
Senior Engineer, Digital Design Engineering
Beaverton, OR · On-site
$121K - $174K/yr
Medical
Dental
Vision
Retirement
PTO
Perform new digital design using Verilog RTL, Standard cells, and similar approaches as necessary for both mixed signal ASIC and FPGA designs. Document design work, present results, and participate ...
Senior Engineer, Digital Design Engineering
Beaverton, OR · On-site
$121K - $174K/yr
Medical
Dental
Vision
Retirement
PTO
Perform new digital design using Verilog RTL, Standard cells, and similar approaches as necessary for both mixed signal ASIC and FPGA designs. Document design work, present results, and participate ...
Principal PCIe Logic Design
Hillsboro, OR · On-site
$108 - $201/hr
Medical
Dental
Retirement
RTL coding: Verilog / System Verilog * Master's degree or PHD in Electrical Engineering, Computer Engineering or equivalent. * 8+ years of experience with RTL Design * Good English skills ...
Principal PCIe Logic Design
Hillsboro, OR · On-site
$108 - $201/hr
Medical
Dental
Retirement
RTL coding: Verilog / System Verilog * Master's degree or PHD in Electrical Engineering, Computer Engineering or equivalent. * 8+ years of experience with RTL Design * Good English skills ...
Preferred Qualifications * 6mths+ experience with Verilog-A/VHDL-A/AMS and mixed signal simulation tools like Cadence* AMS, Mentor* ADMS and/or their equivalent * 6mths+ industry experience in SOC ...
Preferred Qualifications * 6mths+ experience with Verilog-A/VHDL-A/AMS and mixed signal simulation tools like Cadence* AMS, Mentor* ADMS and/or their equivalent * 6mths+ industry experience in SOC ...
Design Verification Principal Engineer
Hillsboro, OR · On-site
$127K - $236K/yr
Medical
Dental
Retirement
System Verilog testbench, Verilog/System Verilog logic design/RTL fluency a must * Pre-existing Experience / familiarity with DDR DRAM technology a strong preference * Working experience with Python ...
Design Verification Principal Engineer
Hillsboro, OR · On-site
$127K - $236K/yr
Medical
Dental
Retirement
System Verilog testbench, Verilog/System Verilog logic design/RTL fluency a must * Pre-existing Experience / familiarity with DDR DRAM technology a strong preference * Working experience with Python ...
Design Verification Principal Engineer
Hillsboro, OR · Hybrid
$127K - $236K/yr
Medical
Dental
Retirement
System Verilog testbench, Verilog/System Verilog logic design/RTL fluency a must * Pre-existing Experience / familiarity with DDR DRAM technology a strong preference * Working experience with Python ...
Design Verification Principal Engineer
Hillsboro, OR · Hybrid
$127K - $236K/yr
Medical
Dental
Retirement
System Verilog testbench, Verilog/System Verilog logic design/RTL fluency a must * Pre-existing Experience / familiarity with DDR DRAM technology a strong preference * Working experience with Python ...
Principal PCIe CXL RTL Design Engineer
Hillsboro, OR · Hybrid
Medical
PTO
RTL coding: Verilog / System Verilog * Master's degree or PHD in Electrical Engineering, Computer Engineering or equivalent. * 5+ years of experience with RTL Design * Good English skills ...
Principal PCIe CXL RTL Design Engineer
Hillsboro, OR · Hybrid
Medical
PTO
RTL coding: Verilog / System Verilog * Master's degree or PHD in Electrical Engineering, Computer Engineering or equivalent. * 5+ years of experience with RTL Design * Good English skills ...
Lead MTS Logic Design
Hillsboro, OR · Hybrid
$111K - $147K/yr
Medical
PTO
RTL coding: Verilog / System Verilog * Master's degree or PHD in Electrical Engineering, Computer Engineering or equivalent. * 7+ years of experience with RTL Design * Good English skills ...
Lead MTS Logic Design
Hillsboro, OR · Hybrid
$111K - $147K/yr
Medical
PTO
RTL coding: Verilog / System Verilog * Master's degree or PHD in Electrical Engineering, Computer Engineering or equivalent. * 7+ years of experience with RTL Design * Good English skills ...
Principal PCIe Logic Design
Hillsboro, OR · Hybrid
$108K - $201K/yr
Medical
Dental
Retirement
RTL coding: Verilog / System Verilog * Master's degree or PHD in Electrical Engineering, Computer Engineering or equivalent. * 8+ years of experience with RTL Design * Good English skills ...
Principal PCIe Logic Design
Hillsboro, OR · Hybrid
$108K - $201K/yr
Medical
Dental
Retirement
RTL coding: Verilog / System Verilog * Master's degree or PHD in Electrical Engineering, Computer Engineering or equivalent. * 8+ years of experience with RTL Design * Good English skills ...
Principal PCIe Logic Design
Hillsboro, OR · On-site
$108K - $201K/yr
Medical
Dental
Retirement
RTL coding: Verilog / System Verilog * Master's degree or PHD in Electrical Engineering, Computer Engineering or equivalent. * 8+ years of experience with RTL Design * Good English skills ...
Principal PCIe Logic Design
Hillsboro, OR · On-site
$108K - $201K/yr
Medical
Dental
Retirement
RTL coding: Verilog / System Verilog * Master's degree or PHD in Electrical Engineering, Computer Engineering or equivalent. * 8+ years of experience with RTL Design * Good English skills ...
Design Verification Principal Engineer
Hillsboro, OR · Hybrid
$127K - $236K/yr
Medical
Dental
Retirement
System Verilog testbench, Verilog/System Verilog logic design/RTL fluency a must * Pre-existing Experience / familiarity with DDR DRAM technology a strong preference * Working experience with Python ...
Design Verification Principal Engineer
Hillsboro, OR · Hybrid
$127K - $236K/yr
Medical
Dental
Retirement
System Verilog testbench, Verilog/System Verilog logic design/RTL fluency a must * Pre-existing Experience / familiarity with DDR DRAM technology a strong preference * Working experience with Python ...
Verilog information
See Oregon salary details
$93K - $104.5K
9% of jobs
$104.5K - $115.9K
2% of jobs
$115.9K - $127.4K
2% of jobs
$127.4K - $138.8K
4% of jobs
$142.9K is the 25th percentile. Wages below this are outliers.
$138.8K - $150.2K
22% of jobs
$150.2K - $161.7K
4% of jobs
The median wage is $173.1K / yr.
$161.7K - $173.1K
6% of jobs
$183.1K is the 75th percentile. Wages above this are outliers.
$173.1K - $184.5K
29% of jobs
$184.5K - $196K
9% of jobs
$196K - $207.4K
6% of jobs
$207.4K - $218.9K
6% of jobs
$93K
$165K
$218.9K
How much do verilog jobs pay per year?
As of Aug 19, 2026, the average yearly pay for verilog in Oregon is $165,018.00, according to ZipRecruiter salary data. Most workers in this role earn between $143,800.00 and $185,600.00 per year, depending on experience, location, and employer.
What is Verilog?
A Verilog job typically involves designing, simulating, and verifying digital circuits using Verilog, a hardware description language (HDL). Engineers in this role work on FPGA and ASIC development for applications such as processors, communication systems, and embedded hardware. Responsibilities often include writing Verilog code, performing design synthesis, and debugging hardware using simulation tools. Verilog engineers are commonly employed in semiconductor, aerospace, and consumer electronics industries.
What does a typical day-to-day workflow look like for someone working with Verilog?
A typical day in a Verilog role involves writing and modifying Verilog code to describe digital circuits, running simulations to verify design functionality, and debugging hardware issues in collaboration with other engineers. You might also interact with hardware engineers, verification teams, and project managers to ensure project milestones are met. Regular review meetings and design documentation are integral parts of the workflow, and you’ll often switch between independent tasks and team-based problem-solving. The work environment is usually dynamic and deadline-driven, offering opportunities to learn about cutting-edge hardware technologies.
What are the key skills and qualifications needed to thrive in the Verilog position, and why are they important?
To excel in a Verilog role, you need a deep understanding of digital logic design, hardware description languages (especially Verilog), and often a degree in electrical or computer engineering. Experience with simulation tools like ModelSim, EDA tools such as Synopsys or Cadence, and potentially industry certifications like FPGA or ASIC design are highly valued. Strong analytical thinking, problem-solving skills, and effective teamwork are important soft skills in this field. These competencies are essential for creating reliable, efficient hardware designs and collaborating within multidisciplinary engineering teams.
What are the most commonly searched types of Verilog jobs in Oregon?
The most popular types of Verilog jobs in Oregon are:
What are popular job titles related to Verilog jobs in Oregon?
For Verilog jobs in Oregon, the most frequently searched job titles are:
What job categories do people searching Verilog jobs in Oregon look for?
The top searched job categories for Verilog jobs in Oregon are:
Job description
Sr/ ASIC Design Engineer
(5+ Years of Experience)
DESCRIPTION OF POSITION/DUTIES -
QUALIFICATIONS -
(5+ Years of Experience)
DESCRIPTION OF POSITION/DUTIES -
- Architect a block of an ASIC and write a microarchitecture specification (MAS) for the block
- Collaborate with other team members to integrate the block with the full chip
- Use Verilog to design and System Verilog for block level verification
- Assist the Verification team in reviewing and debugging test cases
- Run LINT and CDC checks on the RTL code and fix accordingly.
- Assist with synthesis and FPGA emulation.
QUALIFICATIONS -
- BA/MS degree and 5+ years of relevant work experience.
- Demonstrate knowledge of Verilog for chip design and verification.
- Must understand the ASIC flow from MAS to silicon including RTL design, verification, synthesis, timing constraints, GLS, FPGA prototyping, and first silicon bring up and debug.
- Understanding of digital design and verification practices.
- Be able to take a specification, write RTL and simulation vectors to verify their RTL.
- One prior RTL design is a requirement.
- Experience with USB 2.0, USB 3.2, USB4, or PCIe is desired.
About ServerLogic
Sourced by ZipRecruiter
Industry
It services
Company size
11 - 50 Employees
Headquarters location
Tigard, OR, US
Year founded
1992