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Uvm Verification Engineer Jobs in Oregon (NOW HIRING)

Intel

SoC Verification Engineer

Hillsboro, OR

$141K - $200K/yr

Create and update UVM-based test bench generation and test case creation * Define and develop ... developers, postsilicon teams, and physical design teams to improve verification of complex ...

Apple

Design Verification Engineer

Beaverton, OR

$141K - $172K/yr

We have an opportunity for an outstandingly hardworking design verification engineer! As a member ... UVM to stress the design Develop and fix failures from regressions, close bugs Use LLMs to do ...

Apple

Design Verification Engineer

Beaverton, OR

$141K - $172K/yr

We have an opportunity for an outstandingly hardworking design verification engineer! As a member ... UVM to stress the design Develop and fix failures from regressions, close bugs Use LLMs to do ...

Intel

CPU Verification Engineer

Hillsboro, OR

$148K/yr

No one else is obsessed with engineering and has a brighter future. Every day, we create world ... Create scalable verification environments, including UVM-based testbenches and functional coverage ...

Apple

Emulation Verification Engineer

Beaverton, OR

$141K - $172K/yr

... UVM - Develop random stimulus infrastructure by reusing existing UVM simulation constraints ... verification skills Experience in writing Synthesize-able SystemVerilog/Verilog code and ...

Apple

Emulation Verification Engineer

Beaverton, OR

$141K - $172K/yr

... UVM - Develop random stimulus infrastructure by reusing existing UVM simulation constraints ... verification skills Experience in writing Synthesize-able SystemVerilog/Verilog code and ...

Intel

CPU Verification Engineer

Hillsboro, OR

$105K - $200K/yr

Who You Are We are seeking a highly motivated CPU verification engineer to join our design team. In ... Build scalable UVM-based testbenches and define robust functional coverage models. * Run system ...

Nvidia

OR · Hybrid

This includes coding in System Verilog, UVM, C++, Perl, Python and NVIDIA custom compilers and ... Hands on experience in object-oriented programming * Prior design or verification experience at the ...

Apple

Design Verification Engineer

Beaverton, OR · On-site

$141K - $172K/yr

We have an opportunity for an outstandingly hardworking design verification engineer! As a member ... Preferred Qualifications Deep knowledge of OOP, SystemVerilog and UVM Deep knowledge in developing ...

Apple

Design Verification Engineer

Beaverton, OR · On-site

$141K - $172K/yr

We have an opportunity for an outstandingly hardworking design verification engineer! As a member ... UVM Strong knowledge in developing scalable and portable test-benches Proven experience with ...

Intel

Senior CPU Verification Engineer

Hillsboro, OR

$141K - $269K/yr

Who You Are We are seeking a highly motivated senior CPU verification engineer to join our design ... Able to build scalable UVM-based testbenches from and define robust functional coverage models.

K2 Space

OR

$190K - $285K/yr

Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and ... Engineering, or related field. * 10+ years of experience in ASIC/SoC verification. * Solid ...

Apple

Design Verification Engineer

Beaverton, OR · On-site

$141K - $172K/yr

... UVM Experience with C/C++, assembly is a plus. Excellent interpersonal and communication skills and the dream to take on diverse challenges.

Apple

Design Verification Engineer

Beaverton, OR

$141K - $172K/yr

... like UVM Experience with C/C++, assembly is a plus. Excellent interpersonal and communication skills and the dream to take on diverse challenges. Minimum Qualifications Minimum of BS + 10 years ...

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All JobsUvm Verification Engineer JobsUvm Verification Engineer Jobs in Oregon

Uvm Verification Engineer information

See Oregon salary details

$84.6K

$150.8K

$215.2K

How much do uvm verification engineer jobs pay per year?

As of Jul 31, 2026, the average yearly pay for uvm verification engineer in Oregon is $150,789.00, according to ZipRecruiter salary data. Most workers in this role earn between $143,800.00 and $143,800.00 per year, depending on experience, location, and employer.

What is a UVM Verification Engineer job?

A UVM Verification Engineer is responsible for verifying the functionality of digital designs using the Universal Verification Methodology (UVM). They develop testbenches, write SystemVerilog test cases, and implement constrained-random and coverage-driven verification techniques. Their role ensures that ASICs or FPGAs meet design specifications before fabrication. They also work with RTL designers to identify and debug issues, improving overall design quality.

What are the key skills and qualifications needed to thrive in the Uvm Verification Engineer position, and why are they important?

To thrive as a Uvm Verification Engineer, you need a strong background in digital design verification, SystemVerilog programming, and a deep understanding of verification methodologies, particularly Universal Verification Methodology (UVM). Proficiency in using simulation tools such as Mentor Questa, Cadence Xcelium, or Synopsys VCS, as well as familiarity with version control and bug tracking systems, is typically required. Strong analytical thinking, effective communication, and teamwork skills set individuals apart in this position. These skills are crucial to ensure high-quality, reliable silicon designs and seamless collaboration across development teams in fast-paced chip design environments.

What are some typical responsibilities of a Uvm Verification Engineer on a daily basis?

As a Uvm Verification Engineer, your daily responsibilities often include developing and maintaining testbenches using UVM, creating and executing verification plans, writing and debugging test cases in SystemVerilog, and analyzing simulation results to identify design bugs. You’ll typically collaborate closely with design engineers to understand new features and with fellow verification engineers to enhance coverage and test methodology. Regular meetings and status updates are common, ensuring alignment across the verification team and other departments. This dynamic environment offers opportunities to tackle complex debugging challenges and continuously learn as project requirements evolve.

What are popular job titles related to Uvm Verification Engineer jobs in Oregon? For Uvm Verification Engineer jobs in Oregon, the most frequently searched job titles are:
What job categories do people searching Uvm Verification Engineer jobs in Oregon look for? The top searched job categories for Uvm Verification Engineer jobs in Oregon are:
Uvm Verification Engineer jobs near you
Infographic showing various Uvm Verification Engineer job openings in Oregon as of July 2026, with employment types broken down into 82% Full Time, and 18% Contract. Highlights an 91% In-person, and 9% Hybrid job distribution, with an average salary of $150,789 per year, or $72.5 per hour.

SoC Verification Engineer

Intel

Hillsboro, OR

$141K - $200K/yr

Full-time

Medical, Retirement, PTO

Posted 8 days ago

Intel rating

8.7

Company rating: 8.7 out of 10

Based on 147 frontline employees who took The Breakroom Quiz

19th of 156 rated electronics manufacturers

Job description

Job Details:Job Description: About the Team
You will be joining Intel's cutting-edge product development group, a team focused on designing and verifying advanced semiconductor solutions. This group is at the forefront of innovation, delivering high-quality, scalable products that drive Intel's leadership in technology and performance. By contributing your skills here, you will help shape the future of computing and enable groundbreaking advancements in the industry.
Position Overview
As a SoC Design Verification Engineer, you will play a pivotal role in ensuring that Intel's complex System-on-Chip (SoC) designs meet functional specifications and deliver high-quality performance. You will design scalable and reusable verification plans, develop test environments, and execute tests to uncover issues and improve functionality. Your contributions will directly enhance Intel's product quality and ensure optimal performance in presilicon development.
Key Responsibilities
  • Create and update UVM-based test bench generation and test case creation
  • Define and develop scalable and reusable block, subsystem, and SoC verification plans
  • Create test benches and verification environments that align with microarchitecture specifications
  • Execute verification plans, including emulation and system simulation models, to ensure design functionality and uncover bugs
  • Debug and root cause issues in presilicon environments, implementing corrective measures to address failures
  • Collaborate with architects, RTL developers, postsilicon teams, and physical design teams to improve verification of complex architectural features
  • Document and maintain test plans, driving technical reviews with design and architecture teams
  • Integrate security coverage activities within test plans, including regression and debug tests
  • Maintain and improve existing functional verification infrastructure and methodologies
  • Absorb learnings from postsilicon development and incorporate feedback into improved verification strategies
To Be Successful, You Should Demonstrate the Following
  • Ability to work collaboratively across interdisciplinary teams
  • Strong communication skills with the ability to work across interdisciplinary teams
  • Passion for tackling complex problems and delivering innovative solutions
Qualifications:
Minimum Qualifications
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, with 4+ years of hands-on experience in SoC design verification, including demonstrated expertise in OVM/UVM methodologies, debugging, and test planning
    OR
  • Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, with 3+ years of hands-on experience in SoC design verification, including demonstrated expertise in OVM/UVM methodologies, debugging, and test planning
The experience must include:
  • AMBA protocols such as CHI, AXI, AHB, and APB with industry-standard VIP from various EDA vendors
  • Creation and updating of UVM-based test benches and test case creation
Preferred Qualifications
  • Experience with postsilicon validation and incorporating feedback into presilicon test plans
  • Familiarity with emulation models and system simulation tools for performance analysis
We invite you to bring your expertise and creativity to Intel, where your contributions will make a lasting impact on future technology. Join us and shape the future of computing with your skills and dedication.
Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, Texas, AustinAdditional Locations:US, California, Santa Clara, US, Oregon, HillsboroPosting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $141,910.00-200,340.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

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About Intel

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Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth

Industry

Manufacturing

Company size

10,000+ Employees

Headquarters location

Santa Clara, CA, US

Year founded

1968

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