ZipRecruiter

Log In

1

Uvm Verification Engineer Jobs in Oregon (NOW HIRING)

K2 Space

OR

$130K - $200K/yr

Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and ... Engineering, or related field. * 3+ years of experience in ASIC/SoC verification. * Solid ...

Apple

Design Verification Engineer

Beaverton, OR

$141K - $172K/yr

We have an opportunity for an outstandingly hardworking design verification engineer! As a member ... UVM to stress the design Develop and fix failures from regressions, close bugs Use LLMs to do ...

Apple

Design Verification Engineer

Beaverton, OR

$141K - $172K/yr

We have an opportunity for an outstandingly hardworking design verification engineer! As a member ... UVM to stress the design Develop and fix failures from regressions, close bugs Use LLMs to do ...

Apple

Emulation Verification Engineer

Beaverton, OR

$141K - $172K/yr

... UVM - Develop random stimulus infrastructure by reusing existing UVM simulation constraints ... verification skills Experience in writing Synthesize-able SystemVerilog/Verilog code and ...

Apple

Emulation Verification Engineer

Beaverton, OR

$141K - $172K/yr

... UVM - Develop random stimulus infrastructure by reusing existing UVM simulation constraints ... verification skills Experience in writing Synthesize-able SystemVerilog/Verilog code and ...

Nvidia

OR · Hybrid

The NVIDIA Clocks Team is looking for an excellent Senior ASIC Verification engineer with extensive ... This includes coding in System Verilog, UVM, C++, Perl, Python and NVIDIA custom compilers and ...

Intel

CPU Design Verification Engineer

Hillsboro, OR · On-site

$148K - $180K/yr

Create scalable, reusable verification environments using UVM-based testbenches and advanced ... Partner closely with CPU architects, RTL developers, and physical design teams to verify complex ...

Intel

Senior CPU Verification Engineer

Hillsboro, OR

$141K - $269K/yr

Who You Are We are seeking a highly motivated senior CPU verification engineer to join our design ... Able to build scalable UVM-based testbenches from and define robust functional coverage models.

Apple

Design Verification Engineer

Beaverton, OR · On-site

$141K - $172K/yr

We have an opportunity for an outstandingly hardworking design verification engineer! As a member ... Preferred Qualifications Deep knowledge of OOP, SystemVerilog and UVM Deep knowledge in developing ...

Apple

Design Verification Engineer

Beaverton, OR · On-site

$141K - $172K/yr

We have an opportunity for an outstandingly hardworking design verification engineer! As a member ... UVM Strong knowledge in developing scalable and portable test-benches Proven experience with ...

K2 Space

OR · On-site

$190K - $285K/yr

Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and ... Engineering, or related field. * 10+ years of experience in ASIC/SoC verification. * Solid ...

Apple

Design Verification Engineer

Beaverton, OR · On-site

$141K - $172K/yr

... UVM Experience with C/C++, assembly is a plus. Excellent interpersonal and communication skills and the dream to take on diverse challenges.

Apple

Design Verification Engineer

Beaverton, OR

$141K - $172K/yr

... like UVM Experience with C/C++, assembly is a plus. Excellent interpersonal and communication skills and the dream to take on diverse challenges. Minimum Qualifications Minimum of BS + 10 years ...

Nvidia

Senior ASIC Verification Engineer

Hillsboro, OR · On-site

We are now looking for a Senior Verification Engineer for our Memory Management Unit. NVIDIA is ... Experience with Universal Verification Methodology (UVM), SystemVerilog checkers and scoreboards.

next page

Showing results 1-20

All JobsUvm Verification Engineer JobsUvm Verification Engineer Jobs in Oregon

Uvm Verification Engineer information

See Oregon salary details

$84.6K

$150.8K

$215.2K

How much do uvm verification engineer jobs pay per year?

As of Jul 19, 2026, the average yearly pay for uvm verification engineer in Oregon is $150,789.00, according to ZipRecruiter salary data. Most workers in this role earn between $143,800.00 and $143,800.00 per year, depending on experience, location, and employer.

What is a UVM Verification Engineer job?

A UVM Verification Engineer is responsible for verifying the functionality of digital designs using the Universal Verification Methodology (UVM). They develop testbenches, write SystemVerilog test cases, and implement constrained-random and coverage-driven verification techniques. Their role ensures that ASICs or FPGAs meet design specifications before fabrication. They also work with RTL designers to identify and debug issues, improving overall design quality.

What are the key skills and qualifications needed to thrive in the Uvm Verification Engineer position, and why are they important?

To thrive as a Uvm Verification Engineer, you need a strong background in digital design verification, SystemVerilog programming, and a deep understanding of verification methodologies, particularly Universal Verification Methodology (UVM). Proficiency in using simulation tools such as Mentor Questa, Cadence Xcelium, or Synopsys VCS, as well as familiarity with version control and bug tracking systems, is typically required. Strong analytical thinking, effective communication, and teamwork skills set individuals apart in this position. These skills are crucial to ensure high-quality, reliable silicon designs and seamless collaboration across development teams in fast-paced chip design environments.

What are some typical responsibilities of a Uvm Verification Engineer on a daily basis?

As a Uvm Verification Engineer, your daily responsibilities often include developing and maintaining testbenches using UVM, creating and executing verification plans, writing and debugging test cases in SystemVerilog, and analyzing simulation results to identify design bugs. You’ll typically collaborate closely with design engineers to understand new features and with fellow verification engineers to enhance coverage and test methodology. Regular meetings and status updates are common, ensuring alignment across the verification team and other departments. This dynamic environment offers opportunities to tackle complex debugging challenges and continuously learn as project requirements evolve.

What are popular job titles related to Uvm Verification Engineer jobs in Oregon? For Uvm Verification Engineer jobs in Oregon, the most frequently searched job titles are:
What job categories do people searching Uvm Verification Engineer jobs in Oregon look for? The top searched job categories for Uvm Verification Engineer jobs in Oregon are:
Uvm Verification Engineer jobs near you
ASIC Design Verification Engineer (Remote)

ASIC Design Verification Engineer (Remote)

Encore Semi, Inc.

Hillsboro, OR • Remote

$120K - $135K/yr

Full-time

Medical, Dental, Vision, Life, Retirement, PTO

Posted yesterday

New

Job description

ASIC Verification Engineer
Full-time: Salary + Benefits + Bonuses / Contractor
Work Status: US Citizen or Lawful Permanent Resident.
Location: Remote, anywhere in USA
We're seeking a team of mid-level ASIC Verification Engineer to lead verification efforts for next-generation networking and AI accelerator SoCs. In this role, you'll define verification strategies, develop scalable UVM-based environments, drive coverage closure, and ensure high-quality silicon delivery through close collaboration with design, software, emulation, and validation teams.
What You'll Do
  • Lead end-to-end ASIC/SoC verification from planning through coverage and signoff.
  • Build and enhance UVM/SystemVerilog verification environments at block, subsystem, and SoC levels.
  • Create verification plans, develop testcases, execute regressions, and resolve RTL issues.
  • Work cross-functionally with ASIC design, hardware, and post-silicon teams to achieve first-pass silicon success.
  • Mentor engineers, promote verification best practices, and leverage AI-driven tools to improve productivity.

What You'll Bring
  • 4+ years of ASIC/SoC verification experience using SystemVerilog, UVM, VCS, and Verdi (or similar tools).
  • Strong expertise in complex SoC verification, including multi-clock and reset-domain designs.
  • Experience developing verification environments from the ground up.
  • Knowledge of Git/SVN and scripting languages such as Python, Tcl, Perl, or Shell.
  • Proven experience verifying high-speed networking technologies, including 50G/100G/400G Ethernet MAC/PCS, TCP/IP, UDP, RDMA/RoCE, or IPsec.
  • Bachelor’s degree in electrical engineering, Computer Engineering, Computer Science, or a related field (Master's preferred).

The anticipated annual base salary for this position is between $120,000 to $135,000, which also includes a comprehensive benefits package.
Full-Time Benefits:
• 15 days of PTO per calendar year
• 10 paid Holidays per calendar year
• Comprehensive Medical Benefits: Company covers 80% of premiums for Employee and Dependents
• Dental & Vision: Company covers 50% of premiums for Employee and Dependents
• Voluntary Benefits: Life Insurance, FSA (Health and Dependent, Limited Purpose), HAS, and Gap Insurance
• Employee Assistant Program (EAP)
• 401k - Traditional & Roth
• Life/AD&D and Long-Term Disability
• Tuition reimbursement
Equal Opportunity Policy Statement
Encore Semi, Inc. is an Equal Opportunity Employer that does not discriminate on the basis of actual or perceived race, religion, creed, color, age, sex, sexual orientation, gender, gender identity or expression, national origin, genetics, ancestry, marital status, civil union status, medical condition, disability (mental and physical), military and veteran status, pregnancy, childbirth and related medical conditions, or any other characteristic protected by applicable federal, state, or local laws and ordinances.
Encore Semi is also committed to compliance with all fair employment practices regarding citizenship and immigration status.
LinkedIn :: https://www.linkedin.com/in/rtl2gds/