Design Verification Engineer
Beaverton, OR · On-site
$141K - $172K/yr
... UVM Experience with C/C++, assembly is a plus Excellent interpersonal skills and the dream to tackle diverse challenges
Design Verification Engineer
Beaverton, OR · On-site
$141K - $172K/yr
... UVM Experience with C/C++, assembly is a plus Excellent interpersonal skills and the dream to tackle diverse challenges
Design Verification Engineer
$141K - $172K/yr
... like UVM Experience with C/C++, assembly is a plus Excellent interpersonal skills and the dream to tackle diverse challenges Minimum Qualifications Minimum of BS + 3 years relevant industry ...
Design Verification Engineer
$141K - $172K/yr
... like UVM Experience with C/C++, assembly is a plus Excellent interpersonal skills and the dream to tackle diverse challenges Minimum Qualifications Minimum of BS + 3 years relevant industry ...
Design Verification Engineer
Beaverton, OR · On-site
$110 - $170/hr
Design Verification Engineers at Apple are responsible for verifying the functionality and ... Knowledge of verification methodologies like UVM * Experience with C/C++, assembly is a plus
Design Verification Engineer
Beaverton, OR · On-site
$110 - $170/hr
Design Verification Engineers at Apple are responsible for verifying the functionality and ... Knowledge of verification methodologies like UVM * Experience with C/C++, assembly is a plus
IP Design Verification Engineer
Hillsboro, OR · On-site
$141K - $200K/yr
As an IP Verification Engineer, you will be working on UCIe Mixed-Signal IP delivering to multiple ... Test bench development, directed/constrained random test generation in UVM * Closely working with ...
IP Design Verification Engineer
Hillsboro, OR · On-site
$141K - $200K/yr
As an IP Verification Engineer, you will be working on UCIe Mixed-Signal IP delivering to multiple ... Test bench development, directed/constrained random test generation in UVM * Closely working with ...
Senior CPU Pre-Silicon Verification Engineer
Hillsboro, OR · On-site
$164K - $311K/yr
Experience in developing UVM-based testbenches for reusable and scalable verification environments ... Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions ...
Senior CPU Pre-Silicon Verification Engineer
Hillsboro, OR · On-site
$164K - $311K/yr
Experience in developing UVM-based testbenches for reusable and scalable verification environments ... Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions ...
Design Verification Engineer
$184K - $324K/yr
... like UVM Experience with C/C++, assembly is a plus Excellent interpersonal and communication skills and the dream to take on diverse challenges Minimum Qualifications Minimum of BS + 10 years ...
Design Verification Engineer
$184K - $324K/yr
... like UVM Experience with C/C++, assembly is a plus Excellent interpersonal and communication skills and the dream to take on diverse challenges Minimum Qualifications Minimum of BS + 10 years ...
Design Verification Engineer
$184K - $324K/yr
... like UVM Experience with C/C++, assembly is a plus Excellent interpersonal and communication skills and the dream to take on diverse challenges Minimum Qualifications Minimum of BS + 10 years ...
Design Verification Engineer
$184K - $324K/yr
... like UVM Experience with C/C++, assembly is a plus Excellent interpersonal and communication skills and the dream to take on diverse challenges Minimum Qualifications Minimum of BS + 10 years ...
Design Verification Engineer
$184K - $324K/yr
... like UVM Experience with C/C++, assembly is a plus Excellent interpersonal and communication skills and the dream to take on diverse challenges Minimum Qualifications Minimum of BS + 10 years ...
Design Verification Engineer
$184K - $324K/yr
... like UVM Experience with C/C++, assembly is a plus Excellent interpersonal and communication skills and the dream to take on diverse challenges Minimum Qualifications Minimum of BS + 10 years ...
$170K - $250K/yr
Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and ... verification partners when needed. Qualifications * B.S. or M.S. in Electrical Engineering ...
We are now looking for a Verification Engineer for our Memory Management Unit. NVIDIA is seeking ... Experience with Universal Verification Methodology (UVM), SystemVerilog checkers and scoreboards.
We are now looking for a Verification Engineer for our Memory Management Unit. NVIDIA is seeking ... Experience with Universal Verification Methodology (UVM), SystemVerilog checkers and scoreboards.
... UVM base testbenches Experience in system Verilog assertions or silicon bringup or UPF and low ... verification is a plus Advanced programming skills such as object orientated programming or CPU ...
... UVM base testbenches Experience in system Verilog assertions or silicon bringup or UPF and low ... verification is a plus Advanced programming skills such as object orientated programming or CPU ...
Background with System Verilog and UVM based methodology for ASIC verification. Ways to stand out from the crowd: * Strong C/C++ programming experience * Prior Design or Verification experience of ...
Background with System Verilog and UVM based methodology for ASIC verification. Ways to stand out from the crowd: * Strong C/C++ programming experience * Prior Design or Verification experience of ...
... UVM base testbenches Experience in system Verilog assertions or silicon bringup or UPF and low ... verification is a plus Advanced programming skills such as object orientated programming or CPU ...
... UVM base testbenches Experience in system Verilog assertions or silicon bringup or UPF and low ... verification is a plus Advanced programming skills such as object orientated programming or CPU ...
CPU Debug and Power Management Verification Engineer
Beaverton, OR · On-site
$141K/yr
... UVM base testbenches Experience in system Verilog assertions or silicon bringup or UPF and low ... verification is a plus Advanced programming skills such as object orientated programming or CPU ...
CPU Debug and Power Management Verification Engineer
Beaverton, OR · On-site
$141K/yr
... UVM base testbenches Experience in system Verilog assertions or silicon bringup or UPF and low ... verification is a plus Advanced programming skills such as object orientated programming or CPU ...
... UVM base testbenches Experience in system Verilog assertions or silicon bringup or UPF and low ... verification is a plus Advanced programming skills such as object orientated programming or CPU ...
... UVM base testbenches Experience in system Verilog assertions or silicon bringup or UPF and low ... verification is a plus Advanced programming skills such as object orientated programming or CPU ...
CPU Debug and Power Management Verification Engineer
Beaverton, OR · On-site
$141K/yr
... UVM base testbenches Experience in system Verilog assertions or silicon bringup or UPF and low ... verification is a plus Advanced programming skills such as object orientated programming or CPU ...
CPU Debug and Power Management Verification Engineer
Beaverton, OR · On-site
$141K/yr
... UVM base testbenches Experience in system Verilog assertions or silicon bringup or UPF and low ... verification is a plus Advanced programming skills such as object orientated programming or CPU ...
... UVM base testbenches Experience in system Verilog assertions or silicon bringup or UPF and low ... verification is a plus Advanced programming skills such as object orientated programming or CPU ...
... UVM base testbenches Experience in system Verilog assertions or silicon bringup or UPF and low ... verification is a plus Advanced programming skills such as object orientated programming or CPU ...
CPU Debug and Power Management Verification Engineer
Beaverton, OR · On-site
$141K/yr
... UVM base testbenches Experience in system Verilog assertions or silicon bringup or UPF and low ... verification is a plus Advanced programming skills such as object orientated programming or CPU ...
CPU Debug and Power Management Verification Engineer
Beaverton, OR · On-site
$141K/yr
... UVM base testbenches Experience in system Verilog assertions or silicon bringup or UPF and low ... verification is a plus Advanced programming skills such as object orientated programming or CPU ...
CPU Debug and Power Management Verification Engineer
Beaverton, OR · On-site
$141K/yr
... UVM base testbenches Experience in system Verilog assertions or silicon bringup or UPF and low ... verification is a plus Advanced programming skills such as object orientated programming or CPU ...
CPU Debug and Power Management Verification Engineer
Beaverton, OR · On-site
$141K/yr
... UVM base testbenches Experience in system Verilog assertions or silicon bringup or UPF and low ... verification is a plus Advanced programming skills such as object orientated programming or CPU ...
Lead CPU Design Verification Engineer, Silicon
Portland, OR · On-site
$144K/yr
... UVM) and SystemVerilog. * Experience with processor microarchitecture. Preferred qualifications: * Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an ...
Lead CPU Design Verification Engineer, Silicon
Portland, OR · On-site
$144K/yr
... UVM) and SystemVerilog. * Experience with processor microarchitecture. Preferred qualifications: * Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an ...
Uvm Verification Engineer information
See Oregon salary details
$84.6K - $96.5K
1% of jobs
$96.5K - $108.3K
1% of jobs
$108.3K - $120.2K
1% of jobs
$120.2K - $132.1K
1% of jobs
$139.1K is the 25th percentile. Wages below this are outliers.
$132.1K - $143.9K
35% of jobs
The median wage is $146.3K / yr.
$143.9K - $155.8K
54% of jobs
$155.8K - $167.7K
1% of jobs
$167.7K - $179.5K
1% of jobs
$179.5K - $191.4K
2% of jobs
$191.4K - $203.3K
1% of jobs
$203.3K - $215.2K
1% of jobs
$84.6K
$150.8K
$215.2K
How much do uvm verification engineer jobs pay per year?
As of Aug 11, 2026, the average yearly pay for uvm verification engineer in Oregon is $150,789.00, according to ZipRecruiter salary data. Most workers in this role earn between $143,800.00 and $143,800.00 per year, depending on experience, location, and employer.
What is a UVM verification engineer?
A UVM Verification Engineer is responsible for verifying the functionality of digital designs using the Universal Verification Methodology (UVM). They develop testbenches, write SystemVerilog test cases, and implement constrained-random and coverage-driven verification techniques. Their role ensures that ASICs or FPGAs meet design specifications before fabrication. They also work with RTL designers to identify and debug issues, improving overall design quality.
What are the key skills and qualifications needed to thrive as a UVM verification engineer?
To thrive as a Uvm Verification Engineer, you need a strong background in digital design verification, SystemVerilog programming, and a deep understanding of verification methodologies, particularly Universal Verification Methodology (UVM). Proficiency in using simulation tools such as Mentor Questa, Cadence Xcelium, or Synopsys VCS, as well as familiarity with version control and bug tracking systems, is typically required. Strong analytical thinking, effective communication, and teamwork skills set individuals apart in this position. These skills are crucial to ensure high-quality, reliable silicon designs and seamless collaboration across development teams in fast-paced chip design environments.
What are the typical responsibilities of a UVM verification engineer?
As a Uvm Verification Engineer, your daily responsibilities often include developing and maintaining testbenches using UVM, creating and executing verification plans, writing and debugging test cases in SystemVerilog, and analyzing simulation results to identify design bugs. You’ll typically collaborate closely with design engineers to understand new features and with fellow verification engineers to enhance coverage and test methodology. Regular meetings and status updates are common, ensuring alignment across the verification team and other departments. This dynamic environment offers opportunities to tackle complex debugging challenges and continuously learn as project requirements evolve.
What are popular job titles related to Uvm Verification Engineer jobs in Oregon? For Uvm Verification Engineer jobs in Oregon, the most frequently searched job titles are:
What job categories do people searching Uvm Verification Engineer jobs in Oregon look for? The top searched job categories for Uvm Verification Engineer jobs in Oregon are:
$141K - $172K/yr
Full-time
Re-posted 18 days ago
Apple rating
8.0
Based on 677 frontline employees who took The Breakroom Quiz
7th of 30 rated technology retailers
Job description
Does making the next great technology product excite you? Imagine what you could do here. At Apple, our new ideas have a way of becoming great products, services, and customer experiences very quickly. We bring passion and dedication to our job and when you are a part of that team there's no telling what you could accomplish. Design Verification Engineers at Apple are responsible for verifying the functionality and performance of Apple's premier SOCs. This is a critical job within Apple's Hardware Technology and we'd love to have you join us.
Description
As part of a very dedicated team you will be at the heart of the chip design effort collaborating with all subject areas (vertical product model). You own ensuring the quality of the SOC or an IP or subsystem. This requires you to review design and architecture specifications and work closely with design & micro-architecture teams. A key component to the job is understanding the functional & performance goals of the design and you use this knowledge to test optimally. You develop test plans, tests & coverage plans as well as define our next generation verification methodology & testbenches. You will actively communicate and collaborate with design, architecture and software to understand the use cases and corner conditions and drive test cases.
The SOC contains many subsystems and IP, so you may be working on one or several of the following types of IP:
- Neural Engine hardware
- DRAM subsystem, memory controller logic
- Encode and Decode systems for ProRes and other codec formats such as VP9, AV1
- Hardware security, including cryptographic algorithm implementations
- High-Speed IO standards such as PCI Express, DisplayPort, MIPI
- Power management and fabric infrastructure
- Memory cache management
- Display Subsystem for variety of panels and products
These are just some examples of the exciting designs that are part of our team. Joining SOC DV allows you to focus deeply on one main IP or expand your breadth as you work on a collection of subsystems. It's up to you!
Minimum Qualifications
Minimum of BS + 3 years relevant industry experience.
Preferred Qualifications
Methodology & philosophy
Knowledge of SystemVerilog, digital simulation and debug
Knowledge of computer architecture and digital design fundamentals
SW programming skills with knowledge of data structures and algorithms
Experience with Python, Perl, or similar scripting language
Ability to work independently to deliver the project goals
Knowledge of verification methodologies like UVM
Experience with C/C++, assembly is a plus
Excellent interpersonal skills and the dream to tackle diverse challenges
Description
As part of a very dedicated team you will be at the heart of the chip design effort collaborating with all subject areas (vertical product model). You own ensuring the quality of the SOC or an IP or subsystem. This requires you to review design and architecture specifications and work closely with design & micro-architecture teams. A key component to the job is understanding the functional & performance goals of the design and you use this knowledge to test optimally. You develop test plans, tests & coverage plans as well as define our next generation verification methodology & testbenches. You will actively communicate and collaborate with design, architecture and software to understand the use cases and corner conditions and drive test cases.
The SOC contains many subsystems and IP, so you may be working on one or several of the following types of IP:
- Neural Engine hardware
- DRAM subsystem, memory controller logic
- Encode and Decode systems for ProRes and other codec formats such as VP9, AV1
- Hardware security, including cryptographic algorithm implementations
- High-Speed IO standards such as PCI Express, DisplayPort, MIPI
- Power management and fabric infrastructure
- Memory cache management
- Display Subsystem for variety of panels and products
These are just some examples of the exciting designs that are part of our team. Joining SOC DV allows you to focus deeply on one main IP or expand your breadth as you work on a collection of subsystems. It's up to you!
Minimum Qualifications
Minimum of BS + 3 years relevant industry experience.
Preferred Qualifications
Methodology & philosophy
Knowledge of SystemVerilog, digital simulation and debug
Knowledge of computer architecture and digital design fundamentals
SW programming skills with knowledge of data structures and algorithms
Experience with Python, Perl, or similar scripting language
Ability to work independently to deliver the project goals
Knowledge of verification methodologies like UVM
Experience with C/C++, assembly is a plus
Excellent interpersonal skills and the dream to tackle diverse challenges
About Apple
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Cupertino, CA, US
Year founded
1976