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Uvm Verification Engineer Jobs in Oregon (NOW HIRING)

Director, SoC Design Engineering

Hillsboro, OR · On-site

$148K - $180K/yr

... UVM-based verification methodologies and automation flows for improved team productivity. - Lead ... Qualifications: Minimum Qualifications - Bachelor's or BS degree in Electrical Engineering ...

As a Principal Logic Design Engineer , you will play a pivotal role in the micro-architecture and ... UVM Verification experience * Memory (HBM, LPDDR) expertise * AMBA AXI or CHI design experience ...

As a Principal Logic Design Engineer , you will play a pivotal role in the micro-architecture and ... UVM Verification experience * Memory (HBM, LPDDR) expertise * AMBA AXI or CHI design experience ...

Principal Logic Design Engineer

Hillsboro, OR · On-site

$127.40 - $236.60/hr

As a Principal Logic Design Engineer , you will play a pivotal role in the micro-architecture and ... UVM Verification experience * Memory (HBM, LPDDR) expertise * AMBA AXI or CHI design experience ...

As a Principal Logic Design Engineer , you will play a pivotal role in the micro-architecture and ... UVM Verification experience * Memory (HBM, LPDDR) expertise * AMBA AXI or CHI design experience ...

As a Principal Logic Design Engineer , you will play a pivotal role in the micro-architecture and ... UVM Verification experience * Memory (HBM, LPDDR) expertise * AMBA AXI or CHI design experience ...

As a Principal Logic Design Engineer , you will play a pivotal role in the micro-architecture and ... UVM Verification experience * Memory (HBM, LPDDR) expertise * AMBA AXI or CHI design experience ...

As a Principal Logic Design Engineer , you will play a pivotal role in the micro-architecture and ... UVM Verification experience * Memory (HBM, LPDDR) expertise * AMBA AXI or CHI design experience ...

SoC Logic Design Engineer

Hillsboro, OR · On-site

$141K - $232K/yr

... and UVM-based verification. We are looking for innovators passionate about advancing technology ... The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable ...

SoC Logic Design Engineer

Hillsboro, OR · On-site

$141K - $232K/yr

... and UVM-based verification. We are looking for innovators passionate about advancing technology ... The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable ...

Showing results 41-60

Uvm Verification Engineer information

See Oregon salary details

$84.6K

$150.8K

$215.2K

How much do uvm verification engineer jobs pay per year?

As of Aug 12, 2026, the average yearly pay for uvm verification engineer in Oregon is $150,789.00, according to ZipRecruiter salary data. Most workers in this role earn between $143,800.00 and $143,800.00 per year, depending on experience, location, and employer.

What is a UVM verification engineer?

A UVM Verification Engineer is responsible for verifying the functionality of digital designs using the Universal Verification Methodology (UVM). They develop testbenches, write SystemVerilog test cases, and implement constrained-random and coverage-driven verification techniques. Their role ensures that ASICs or FPGAs meet design specifications before fabrication. They also work with RTL designers to identify and debug issues, improving overall design quality.

What are the key skills and qualifications needed to thrive as a UVM verification engineer?

To thrive as a Uvm Verification Engineer, you need a strong background in digital design verification, SystemVerilog programming, and a deep understanding of verification methodologies, particularly Universal Verification Methodology (UVM). Proficiency in using simulation tools such as Mentor Questa, Cadence Xcelium, or Synopsys VCS, as well as familiarity with version control and bug tracking systems, is typically required. Strong analytical thinking, effective communication, and teamwork skills set individuals apart in this position. These skills are crucial to ensure high-quality, reliable silicon designs and seamless collaboration across development teams in fast-paced chip design environments.

What are the typical responsibilities of a UVM verification engineer?

As a Uvm Verification Engineer, your daily responsibilities often include developing and maintaining testbenches using UVM, creating and executing verification plans, writing and debugging test cases in SystemVerilog, and analyzing simulation results to identify design bugs. You’ll typically collaborate closely with design engineers to understand new features and with fellow verification engineers to enhance coverage and test methodology. Regular meetings and status updates are common, ensuring alignment across the verification team and other departments. This dynamic environment offers opportunities to tackle complex debugging challenges and continuously learn as project requirements evolve.

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What job categories do people searching Uvm Verification Engineer jobs in Oregon look for? The top searched job categories for Uvm Verification Engineer jobs in Oregon are:
Infographic showing various Uvm Verification Engineer job openings in Oregon as of August 2026, with employment types broken down into 87% Full Time, 6% Part Time, 6% Contract, and 1% Nights. Highlights an 86% Physical, 5% Hybrid, and 9% Remote job distribution, with an average salary of $150,789 per year, or $72.5 per hour.

Senior Engineer Design Verification Engineering

Analog Devices

Beaverton, OR • On-site

$119K - $163K/yr

Full-time

Medical, Dental, Vision, Retirement, PTO

Re-posted 16 hours ago


Analog Devices rating

8.5

Company rating: 8.5 out of 10

Based on 17 frontline employees who took The Breakroom Quiz

33rd of 157 rated electronics manufacturers


Job description

About Analog Devices
Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at www.analog.com and on LinkedIn and Twitter (X).
Employer: Analog Devices, Inc.
Job Title: Senior Engineer Design Verification Engineering
Job Requisition: 1010.1272.5 / R262669
Job Location: Beaverton, Oregon
Job Type: Full Time
Rate of Pay: $119,475 - $163,200 per year
[multiple openings]
Duties: Support and accelerate product development of industry leading products involving behavioral modeling of analog circuits, spice, and mixed-signal verification; full-chip verification; and digital circuit verification. Establish and promote the adoption of metric-driven verification best practices. Leverage complex digital and mixed-signal circuits and create self-checking test benches to validate designs before production. Work with analog, digital, and mixed-signal design engineers to create state-of-the-art models of mixed-signal ICs. Apply verification methodologies to reach verification goals, including creating System Verilog simulation environments and infrastructure to verify functionality, accuracy, and performance and integrate models into full-chip simulations. Create scripts using scripting languages to analyze simulation data, validate models, and build simulation test benches. Correlate results with multidisciplinary teams involved in the design. Support design teams in identifying, debugging, and resolving issues. Assist in developing project verification strategies, planning, resource tracking, and results analysis, to ensure on-schedule product delivery.
Partial telecommute benefit (2 days/week work from home).
Requirements: Must have a Master's degree in Computer Science, Computer Engineering, Electrical Engineering, Electronic Engineering, or closely related technical field (willing to accept foreign education equivalent) and two (2) years of experience as a Design Verification Engineer or related occupation performing IC design or validation.
Or in the alternative, a Bachelor's degree in Computer Science, Computer Engineering, Electrical Engineering, Electronic Engineering, or closely related technical field (willing to accept foreign education equivalent) and four (4) years of experience as a Design Verification Engineer or related occupation performing IC design or validation.
Must also possess the following (quantitative experience requirements not applicable to this section):
  • Demonstrated expertise (DE) in Perl or Python scripting for data processing, data design creation, data collection, analysis, design automation tools controls, and input/output data formatting.
  • DE executing the full-lifecycle of design/verification, including verification planning, test bench and test case development, architecting coverage and performing system debugging utilizing Cadence Xcelium simulator suite, Synopsys VCS or equivalent.
  • DE driving metric-driven verification, including specifying, developing, and leveraging advanced verification capabilities using System Verilog, UVM, and coverage analysis.
  • Demonstrated understanding of analog and digital circuits through prior work experience and coursework.
  • DE eliciting and communicating complex technical details before key stakeholders.

Contact: Eligible for employee referral program. Apply online at https://www.analog.com/en/careers.html and Reference Position Number: R262669.
For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position - except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) - may have to go through an export licensing review process.
Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.
EEO is the Law: Notice of Applicant Rights Under the Law.
Job Req Type: Experienced
Required Travel: No
Shift Type: 1st Shift/Days
  • Actual wage offered may vary depending on work location, experience, education, training, external market data, internal pay equity, or other bona fide factors.
  • This position qualifies for a discretionary performance-based bonus which is based on personal and company factors.
  • This position includes medical, vision and dental coverage, 401k, paid vacation, holidays, and sick time, and other benefits.

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About Analog Devices

Sourced by ZipRecruiter

Analog Devices (NASDAQ: ADI) designs and manufactures semiconductor products and solutions. We enable our customers to interpret the world around us by intelligently bridging the physical and digital worlds with unmatched technologies that sense, measure and connect.

Industry

Electrical equipment, appliance, and component manufacturing

Company size

5,001 - 10,000 Employees

Headquarters location

Norwood, MA, US

Year founded

1965