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Uvm Verification Engineer Jobs in Oregon (NOW HIRING)

Intel

Director, SoC Design Engineering

Hillsboro, OR

$148K - $180K/yr

... UVM-based verification methodologies and automation flows for improved team productivity. - Lead ... Qualifications: Minimum Qualifications - Bachelor's or BS degree in Electrical Engineering ...

Rambus

Principal Logic Design Engineer

Hillsboro, OR · Hybrid

$127K - $236K/yr

As a Principal Logic Design Engineer , you will play a pivotal role in the micro-architecture and ... UVM Verification experience * Memory (HBM, LPDDR) expertise * AMBA AXI or CHI design experience ...

Rambus

Principal Logic Design Engineer

Hillsboro, OR · Hybrid

$127K - $236K/yr

As a Principal Logic Design Engineer , you will play a pivotal role in the micro-architecture and ... UVM Verification experience * Memory (HBM, LPDDR) expertise * AMBA AXI or CHI design experience ...

Rambus.com

Principal Logic Design Engineer

Hillsboro, OR · On-site

$127.40 - $236.60/hr

As a Principal Logic Design Engineer , you will play a pivotal role in the micro-architecture and ... UVM Verification experience * Memory (HBM, LPDDR) expertise * AMBA AXI or CHI design experience ...

Rambus

Principal Logic Design Engineer

Hillsboro, OR · On-site

$127K - $236K/yr

As a Principal Logic Design Engineer , you will play a pivotal role in the micro-architecture and ... UVM Verification experience * Memory (HBM, LPDDR) expertise * AMBA AXI or CHI design experience ...

Rambus

Principal Logic Design Engineer

Hillsboro, OR · On-site

$127K - $236K/yr

As a Principal Logic Design Engineer , you will play a pivotal role in the micro-architecture and ... UVM Verification experience * Memory (HBM, LPDDR) expertise * AMBA AXI or CHI design experience ...

Rambus

Principal Logic Design Engineer

Hillsboro, OR · Hybrid

$127K - $236K/yr

As a Principal Logic Design Engineer , you will play a pivotal role in the micro-architecture and ... UVM Verification experience * Memory (HBM, LPDDR) expertise * AMBA AXI or CHI design experience ...

Rambus

Principal Logic Design Engineer

Hillsboro, OR · Hybrid

$127K - $236K/yr

As a Principal Logic Design Engineer , you will play a pivotal role in the micro-architecture and ... UVM Verification experience * Memory (HBM, LPDDR) expertise * AMBA AXI or CHI design experience ...

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Uvm Verification Engineer information

See Oregon salary details

$84.6K

$150.8K

$215.2K

How much do uvm verification engineer jobs pay per year?

As of Aug 14, 2026, the average yearly pay for uvm verification engineer in Oregon is $150,789.00, according to ZipRecruiter salary data. Most workers in this role earn between $143,800.00 and $143,800.00 per year, depending on experience, location, and employer.

What is a UVM verification engineer?

A UVM Verification Engineer is responsible for verifying the functionality of digital designs using the Universal Verification Methodology (UVM). They develop testbenches, write SystemVerilog test cases, and implement constrained-random and coverage-driven verification techniques. Their role ensures that ASICs or FPGAs meet design specifications before fabrication. They also work with RTL designers to identify and debug issues, improving overall design quality.

What are the key skills and qualifications needed to thrive as a UVM verification engineer?

To thrive as a Uvm Verification Engineer, you need a strong background in digital design verification, SystemVerilog programming, and a deep understanding of verification methodologies, particularly Universal Verification Methodology (UVM). Proficiency in using simulation tools such as Mentor Questa, Cadence Xcelium, or Synopsys VCS, as well as familiarity with version control and bug tracking systems, is typically required. Strong analytical thinking, effective communication, and teamwork skills set individuals apart in this position. These skills are crucial to ensure high-quality, reliable silicon designs and seamless collaboration across development teams in fast-paced chip design environments.

What are the typical responsibilities of a UVM verification engineer?

As a Uvm Verification Engineer, your daily responsibilities often include developing and maintaining testbenches using UVM, creating and executing verification plans, writing and debugging test cases in SystemVerilog, and analyzing simulation results to identify design bugs. You’ll typically collaborate closely with design engineers to understand new features and with fellow verification engineers to enhance coverage and test methodology. Regular meetings and status updates are common, ensuring alignment across the verification team and other departments. This dynamic environment offers opportunities to tackle complex debugging challenges and continuously learn as project requirements evolve.

What are popular job titles related to Uvm Verification Engineer jobs in Oregon?

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What job categories do people searching Uvm Verification Engineer jobs in Oregon look for?

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Uvm Verification Engineer jobs near you
Infographic showing various Uvm Verification Engineer job openings in Oregon as of August 2026, with employment types broken down into 87% Full Time, 6% Part Time, 6% Contract, and 1% Nights. Highlights an 86% Physical, 5% Hybrid, and 9% Remote job distribution, with an average salary of $150,789 per year, or $72.5 per hour.

Senior Fabric Design Verification Engineer

Microsoft

Hillsboro, OR • On-site

$113K - $156K/yr

Full-time

Posted 22 days ago

Microsoft rating

8.5

Company rating: 8.5 out of 10

Based on 132 frontline employees who took The Breakroom Quiz

79th of 244 rated software companies

Job description

Overview
Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft's expanding Cloud Infrastructure and responsible for powering Microsoft's "Intelligent Cloud" mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for a Senior Fabric Design Verification Engineer to help achieve that mission.
The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE is responsible for design, development, manufacturing and packaging of Microsoft's state-of-the-art computer chips, notably the Azure Cobalt. Our solutions provide sustainable strategic advantage to Microsoft and enable our customers to achieve more.
As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the CSME team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for a Senior Fabric Design Verification engineer for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.
We are looking for a Senior Fabric Design Verification Engineer to join the team.
Responsibilities
The candidate for this position will be expected and able to complete the following responsibilities:
  • Own or lead verification of complex flows at fabric interconnect or at block level
  • Learn about the design and interact with partner teams to define verification strategies and test plans
  • Develop UVM-based verification environments and run and debug simulations to drive quality
  • Apply random-stimulus and coverage-based techniques to find bugs and meet test plan goals
  • Innovate to improve verification efficiency through methodologies or tools
  • Apply industry leading generative AI solutions to verification work
  • Share expertise and support the growth and development of others through coaching, mentorship, and collaboration.
  • Demonstrate Microsoft core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement, and Diversity & Inclusion

Qualifications
Required Qualifications:
  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience.

Other Requirements
  • Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
  • This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate's citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.

Preferred Qualifications:
  • 5+ years of pre-silicon subsystem or IP verification experience.
  • 7+ years of related technical engineering experience
    • OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience or internship experience
    • OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ year(s) technical engineering experience or internship experience.
    • OR Doctorate degree in Electrical Engineering, Computer Science, Computer Engineering, or related field.
  • Demonstrated experience in verifying designs that utilize Coherent Hub Interface (CHI) and Advanced Microcontroller Bus Architecture (AMBA) protocols.
  • Demonstrated experience in one or more of the following: fabric interconnects, coherency, virtualization, security, interrupts, PCIe, CXL, and/or protocol bridges.
  • Experience driving IP verification for a full product cycles from definition to silicon, including writing IP/block or subsystem level test plans, developing tests, debugging failures and coverage signoff.
  • Demonstrated hands-on technical leadership such as creating bottom's up schedules, coordinating work across a team, driving verification closure, or solving cross-team technical problems.
  • Experience creating, maintaining, or integrating test benches, checkers and stimulus using Universal Verification Methodology (UVM), System Verilog Test Bench (SVTB), and optionally Python based post-processing checking.
  • Aptitude for writing scripts/software with industry standard languages like Python.
  • Experience applying generative AI to day-to-day tasks.

#SCHIE #CSME
Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $160,200 - $261,000 per year.
Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:
https://careers.microsoft.com/us/en/us-corporate-pay
This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.
Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.

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About Microsoft

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Our infrastructure is comprised of a large global portfolio of more than 100 datacenters and 1 million servers. Our foundation is built upon and managed by a team of subject matter experts working to support services for more than 1 billion customers and 20 million businesses in over 90 countries worldwide. With environmental sustainability and optimization at the forefront of our datacenter design and operations, we continue to grow and evolve as we meet the ever-changing business demands that hold Microsoft as a world-class cloud provider.

Industry

Computer and computer peripheral equipment and software wholesalers

Company size

10,000+ Employees

Headquarters location

Redmond, WA, US

Year founded

1975

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