ZipRecruiter

Log In

1

Uvm Verification Engineer Jobs (NOW HIRING)

Airspan

UVM SYSTEMVERILOG VERIFICATION ENGINEER

Warren, NJ · On-site

$141.20K/yr

Airspan Careers UVM SYSTEMVERILOG VERIFICATION ENGINEER Location: Warren, New Jersey, Plano, TX or REMOTE U.S. Company: AirSpan Networks About AirSpan AirSpan Networks is a global provider of ...

Correct Designs

Design Verification Engineer

Austin, TX

$134.80K - $164.50K/yr

Correct Designs is currently seeking talented Verification Engineers with prior System Verilog UVM experience to work with our major clients both in Austin, TX, and nationwide. Opportunities span ...

Correct Designs

Design Verification Engineer

Austin, TX

$134.80K - $164.50K/yr

Correct Designs is currently seeking talented Verification Engineers with prior System Verilog UVM experience to work with our major clients both in Austin, TX, and nationwide. Opportunities span ...

Saransh Inc

FPGA Verification Engineer

Mountain View, CA · On-site

$153.40K - $197K/yr

FPGA Verification Engineer Location: Mountain View, CA (Onsite from Day 1) Contract Must Have ... Proficiency in System Verilog and UVM verification methodology * Experience in FPGA verification ...

Embtel Inc

Design Verification Engineer (Remote)

Sunnyvale, CA · On-site

$159.60K - $194.80K/yr

Design Verification Engineer Locations : Sunnyvale, CA (Remote) No. of positions: 09 Duration: 6+ ... Building a test bench for a block using System Verilog and UVM Writing random tests, directed tests ...

Correct Designs

Design Verification Engineer

Austin, TX · On-site

$134.80K - $164.50K/yr

Correct Designs is currently seeking talented Verification Engineers with prior System Verilog UVM experience to work with our major clients both in Austin, TX, and nationwide. Opportunities span ...

Correct Designs

Design Verification Engineer

Austin, TX · On-site

$134.80K - $164.50K/yr

Correct Designs is currently seeking talented Verification Engineers with prior System Verilog UVM experience to work with our major clients both in Austin, TX, and nationwide. Opportunities span ...

Correct Designs

Senior Design Verification Engineer

Austin, TX · On-site

$131.30K - $160.30K/yr

Correct Designs is currently seeking talented Verification Engineers with prior System Verilog UVM experience to work with our major clients both in Austin, TX, and nationwide. Opportunities span ...

Correct Designs

Senior Design Verification Engineer

Austin, TX · On-site

$134.80K - $164.50K/yr

Correct Designs is currently seeking talented Verification Engineers with prior System Verilog UVM experience to work with our major clients both in Austin, TX, and nationwide. Opportunities span ...

next page

Showing results 1-20

People also search for

All JobsUvm Verification Engineer Jobs

Uvm Verification Engineer information

See salary details

$80K

$142.6K

$203.5K

How much do uvm verification engineer jobs pay per year?

As of May 31, 2026, the average yearly pay for uvm verification engineer in the United States is $142,619.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $136,000.00 per year, depending on experience, location, and employer.

What is a UVM Verification Engineer job?

A UVM Verification Engineer is responsible for verifying the functionality of digital designs using the Universal Verification Methodology (UVM). They develop testbenches, write SystemVerilog test cases, and implement constrained-random and coverage-driven verification techniques. Their role ensures that ASICs or FPGAs meet design specifications before fabrication. They also work with RTL designers to identify and debug issues, improving overall design quality.

What are the key skills and qualifications needed to thrive in the Uvm Verification Engineer position, and why are they important?

To thrive as a Uvm Verification Engineer, you need a strong background in digital design verification, SystemVerilog programming, and a deep understanding of verification methodologies, particularly Universal Verification Methodology (UVM). Proficiency in using simulation tools such as Mentor Questa, Cadence Xcelium, or Synopsys VCS, as well as familiarity with version control and bug tracking systems, is typically required. Strong analytical thinking, effective communication, and teamwork skills set individuals apart in this position. These skills are crucial to ensure high-quality, reliable silicon designs and seamless collaboration across development teams in fast-paced chip design environments.

What are some typical responsibilities of a Uvm Verification Engineer on a daily basis?

As a Uvm Verification Engineer, your daily responsibilities often include developing and maintaining testbenches using UVM, creating and executing verification plans, writing and debugging test cases in SystemVerilog, and analyzing simulation results to identify design bugs. You’ll typically collaborate closely with design engineers to understand new features and with fellow verification engineers to enhance coverage and test methodology. Regular meetings and status updates are common, ensuring alignment across the verification team and other departments. This dynamic environment offers opportunities to tackle complex debugging challenges and continuously learn as project requirements evolve.
More about Uvm Verification Engineer jobs
What states have the most Uvm Verification Engineer jobs? States with the most job openings for Uvm Verification Engineer jobs include:
What job categories do people searching Uvm Verification Engineer jobs look for? The top searched job categories for Uvm Verification Engineer jobs are:
Uvm Verification Engineer jobs near you
Infographic showing various Uvm Verification Engineer job openings in the United States as of May 2026, with employment types broken down into 85% Full Time, 6% Part Time, and 9% Contract. Highlights an 8% Physical, and 92% Remote job distribution, with an average salary of $142,619 per year, or $68.6 per hour.

UVM SYSTEMVERILOG VERIFICATION ENGINEER

Airspan

Warren, NJ • On-site

$141.20K/yr

Full-time

Posted 21 days ago

Job description

Airspan Careers
UVM SYSTEMVERILOG VERIFICATION ENGINEER
Location: Warren, New Jersey, Plano, TX or REMOTE U.S.
Company: AirSpan Networks
About AirSpan
AirSpan Networks is a global provider of innovative 4G and 5G network solutions, enabling efficient and cost-effective connectivity for operators, enterprises, and industrial applications. We are looking for a skilled UVM SystemVerilog Verification Engineer to join our dynamic team and contribute to the validation and testing of our cutting-edge communication technologies.
Job Description
As a UVM Verification Engineer, you will be responsible for developing and executing test plans using Universal Verification Methodology (UVM) to validate the functionality, performance, and reliability of AirSpan's ASIC and FPGA designs. You will work closely with design and development teams to ensure compliance with specifications and industry standards.
Key Responsibilities
  • Develop and implement UVM-based verification plans and test strategies for FPGA designs.
  • Perform functional, system-level, and regression testing for digital hardware components.
  • Create test benches, test cases, and automation frameworks in System Verilog.
  • Analyze test results, debug issues, and collaborate with design teams to resolve defects.
  • Ensure compliance with industry standards and customer requirements.
  • Provide documentation and reports on test procedures, results, and defect tracking.
  • Continuously optimize test processes and tools to improve efficiency and accuracy.

Qualifications & Experience
  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related fields.
  • 10 years of experience in UVM-based verification of FPGA systems.
  • Strong understanding of SystemVerilog and Universal Verification Methodology (UVM).
  • Proficiency in scripting languages such as Python or Perl for automation.
  • Experience with simulation tools such as ModelSim or QuestaSim.
  • Experience with C/C++
  • Experience in implementing Bit Accurate Models and debugging DSP designs
  • Familiarity with debugging tools, coverage metrics, and formal verification techniques.
  • Strong problem-solving and analytical skills with attention to detail.
  • Knowledge of O-RAN architecture and protocols for 4G and 5G networks.
  • Ability to work collaboratively in a fast-paced, cross-functional team environment.
  • Design experience a plus.

Preferred Skills
  • Experience in verification of communication protocols.
  • Knowledge of FPGA development and hardware description languages such as VHDL/Verilog.
  • Understanding of hardware/software co-verification techniques.

Apply