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Design Verification Jobs (NOW HIRING)

Design Verification UVM

Santa Clara, CA · On-site

$158K - $193K/yr

Design Verification 1-2 Spots Sunnyvale, CA or Austin TX- Onsite is a must. Main thing is STONG UVM -Networking, ethernet protocols -Python is a plus Here is the JD Responsibilities * Define and ...

Design Verification Lead

Huntsville, AL · On-site

$134K - $163K/yr

Design Verification Lead Location: Huntsville, AL / Richmond, VA Summary: Seeking an experienced Design Verification Lead to support the construction and startup of a pharmaceutical manufacturing ...

Design Verification Engineer

Austin, TX · On-site

$134K - $164K/yr

Design Verification Engineer ID: 1063 Location: Austin, TX More about this job > Description Design Verification Engineer Looking for new challenges? Would you like the variety of a contract position ...

Design Verification Engineer

Austin, TX

$134K - $164K/yr

Design Verification Engineer ID: 1058 Location: Austin, TX More about this job > Description Design Verification Engineer Looking for new challenges? Would you like the variety of a contract position ...

Design Verification Engineer

Fort Collins, CO · On-site

$134K - $164K/yr

Lead ASIC Design Verification Engineer We are seeking a highly experienced and visionary Lead/Principal ASIC Design Verification Engineer to drive the verification strategy for our next-generation ...

Design Verification Engineer

Fort Collins, CO · On-site

$134K - $164K/yr

Lead ASIC Design Verification Engineer We are seeking a highly experienced and visionary Lead/Principal ASIC Design Verification Engineer to drive the verification strategy for our next-generation ...

Design Verification Engineer

Austin, TX · On-site

$134K - $164K/yr

Description As a Design Verification Engineer, you'll be at the center of our silicon design group's verification efforts, ensuring the quality and reliability of next-generation cellular systems.

We're hiring experienced Design Verification Engineers from junior to senior levels to play a key role in developing and verifying the designs that will bring our next-generation AI processors to ...

Design Verification Engineer

Austin, TX · On-site

$134K - $164K/yr

Description As a Design Verification Engineer, you'll be at the center of our silicon design group's verification efforts, ensuring the quality and reliability of next-generation cellular systems.

Description As a Design Verification Engineer, you'll be at the center of our silicon design group's verification efforts, ensuring the quality and reliability of next-generation cellular systems.

Description As a Design Verification Engineer, you'll be at the center of our silicon design group's verification efforts, ensuring the quality and reliability of next-generation cellular systems.

Design Verification Engineer

Denver, CO · On-site

$167K - $184K/yr

Design Verification Engineer Develop strategies for verification by understanding design architecture and design specifications. Capture all requirements/features of design to create functional ...

We're hiring experienced Design Verification Engineers from junior to senior levels to play a key role in developing and verifying the designs that will bring our next-generation AI processors to ...

We're hiring experienced Design Verification Engineers from junior to senior levels to play a key role in developing and verifying the designs that will bring our next-generation AI processors to ...

Design Verification Engineer

Austin, TX · On-site

$120K - $225K/yr

We're hiring experienced Design Verification Engineers from junior to senior levels to play a key role in developing and verifying the designs that will bring our next-generation AI processors to ...

Design Verification Engineer

Austin, TX · On-site

$120K - $225K/yr

We're hiring experienced Design Verification Engineers from junior to senior levels to play a key role in developing and verifying the designs that will bring our next-generation AI processors to ...

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Design Verification information

See salary details

$105.5K

$149.2K

$167K

How much do design verification jobs pay per year?

As of Jul 31, 2026, the average yearly pay for design verification in the United States is $149,150.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $166,000.00 per year, depending on experience, location, and employer.

What is the difference between Design Verification vs Design Validation?

AspectDesign VerificationDesign Validation
PurposeEnsures the design meets specified requirements through testing and analysisConfirms the final product fulfills user needs and intended use
TimingDuring the development phaseAfter the product is developed and before release
MethodsInspections, reviews, testing, analysisUser testing, field trials, real-world testing
FocusDesign correctness and complianceProduct effectiveness and user satisfaction

While Design Verification checks if the design meets specified requirements during development, Design Validation ensures the final product performs effectively in real-world conditions. Both are essential steps in the product development process to deliver a reliable and user-centered product.

What are design verification engineers?

Design verification engineers are professionals who ensure that hardware or software designs meet their intended specifications and function correctly before production or release. They develop and execute tests, write verification plans, create simulation environments, and identify design flaws or errors. Their work is critical in industries like semiconductor, electronics, and software development to prevent costly mistakes and ensure high-quality products. Design verification engineers often work closely with design and validation teams throughout the product development lifecycle.

What are the key skills and qualifications needed to thrive as a Design Verification Engineer, and why are they important?

To thrive as a Design Verification Engineer, you need a solid background in digital design, verification methodologies, and programming languages like SystemVerilog, typically supported by a degree in electrical engineering or a related field. Familiarity with verification tools such as UVM, simulation environments, and EDA software is essential, along with knowledge of scripting languages like Python or Perl. Strong analytical thinking, attention to detail, and effective teamwork are standout soft skills in this role. These skills ensure accurate validation of complex hardware designs, reducing errors and supporting reliable product development cycles.

What are some common challenges faced by Design Verification engineers, and how can they be addressed?

Design Verification engineers often encounter challenges such as managing complex testbenches, debugging intricate corner cases, and ensuring coverage completeness within tight project timelines. To address these, it’s important to have strong scripting skills, collaborate closely with design and validation teams, and make effective use of verification methodologies like UVM. Regular communication and review cycles also help catch issues early and improve overall verification quality.
More about Design Verification jobs
What cities are hiring for Design Verification jobs? Cities with the most Design Verification job openings:
What are the most commonly searched types of Design Verification jobs? The most popular types of Design Verification jobs are:
What states have the most Design Verification jobs? States with the most job openings for Design Verification jobs include:
Infographic showing various Design Verification job openings in the United States as of July 2026, with employment types broken down into 88% Full Time, 9% Part Time, and 3% Contract. Highlights an 85% Physical, 4% Hybrid, and 11% Remote job distribution, with an average salary of $149,150 per year, or $71.7 per hour.

Design Verification UVM

Technical Link

Santa Clara, CA • On-site

$158K - $193K/yr

Other

Posted 24 days ago


Job description

Design Verification 

1-2 Spots

Sunnyvale, CA or Austin TX- Onsite is a must.

Main thing is STONG UVM

-Networking, ethernet protocols

-Python is a plus

Here is the JD
Responsibilities

  • Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification
  • Develop functional tests based on verification test plan
  • Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
  • Debug, root-cause, and resolve functional failures in the design, partnering with the Design team
  • Collaborate with cross-functional teams like Design, Model, Emulation, and Silicon validation teams towards ensuring the highest design quality

Minimum Qualifications

  • B.S or M.S degree in Electrical Engineering, Computer Engineering or Computer Science
  • Hands-on experience in Verilog, SystemVerilog, C/C++ based verification, and UVM methodology
  • Experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies
  • Experience in EDA tools and scripting (Python, Perl, Shell) used to build tools and flows for verification environments.
  • Experience in architecting and implementing Design Verification infrastructure and executing the complete verification cycle

Preferred Qualifications

  • Experience in the development of UVM based verification environments from scratch
  • Experience with Design verification of Data-center applications like Video, AI/ML, and Networking designs
  • Experience with revision control systems like Mercurial(Hg), Git or SVN
  • Experience with verification of ARM/RISC-V based sub-systems or SoCs