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Design Verification Jobs (NOW HIRING)

HCP ONE LLC

Design Verification Engineer

San Jose, CA · On-site

$159K - $194K/yr

Design Verification Engineer Location: San Jose, CA Experience: 8+ Years Type: Contract Description: This requirement is for a Senior Design Verification (DV) Engineer focused on verifying complex ...

Correct Designs

Design Verification Engineer

Austin, TX · On-site

$134K - $164K/yr

Design Verification Engineer ID: 1063 Location: Austin, TX More about this job > Description Design Verification Engineer Looking for new challenges? Would you like the variety of a contract position ...

Sivaltech

Design Verification Engineer

San Diego, CA · On-site

$144K - $176K/yr

Design Verification Engineer Location: Bay Area, CA (Onsite/Hybrid) Experience: 8+ Years Job Summary We are seeking an experienced Design Verification Engineer with strong expertise in ASIC/SoC ...

Correct Designs

Design Verification Engineer

Austin, TX · On-site

$134K - $164K/yr

Design Verification Engineer ID: 1058 Location: Austin, TX More about this job > Description Design Verification Engineer Looking for new challenges? Would you like the variety of a contract position ...

Apple

Design Verification Engineer

Austin, TX · On-site

$134K - $164K/yr

Description As a Design Verification Engineer, you'll be at the center of our silicon design group's verification efforts, ensuring the quality and reliability of next-generation cellular systems.

Mythic

Design Verification Engineer

Palo Alto, CA · On-site

$120K - $225K/yr

We're hiring experienced Design Verification Engineers from junior to senior levels to play a key role in developing and verifying the designs that will bring our next-generation AI processors to ...

Mythic

Design Verification Engineer

Austin, TX · On-site

$120K - $225K/yr

We're hiring experienced Design Verification Engineers from junior to senior levels to play a key role in developing and verifying the designs that will bring our next-generation AI processors to ...

Apple

Design Verification Engineer

Austin, TX · On-site

$134K - $164K/yr

Description As a Design Verification Engineer, you'll be at the center of our silicon design group's verification efforts, ensuring the quality and reliability of next-generation cellular systems.

Mythic

Design Verification Engineer

Palo Alto, CA · On-site

$120K - $225K/yr

We're hiring experienced Design Verification Engineers from junior to senior levels to play a key role in developing and verifying the designs that will bring our next-generation AI processors to ...

Mythic

Design Verification Engineer

Austin, TX · On-site

$120K - $225K/yr

We're hiring experienced Design Verification Engineers from junior to senior levels to play a key role in developing and verifying the designs that will bring our next-generation AI processors to ...

Hobbsnews

Design Verification Manager

Sunnyvale, CA · On-site

$174 - $352.50/hr

Design Verification Manager Who We Are: Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on ...

New

Apple

Design Verification Engineer

Austin, TX

$122K - $214K/yr

Description As a Design Verification Engineer, you'll be at the center of our silicon design group's verification efforts, ensuring the quality and reliability of next-generation cellular systems.

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Design Verification information

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$105.5K

$149.2K

$167K

How much do design verification jobs pay per year?

As of Aug 21, 2026, the average yearly pay for design verification in the United States is $149,150.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $166,000.00 per year, depending on experience, location, and employer.

What is a design verification engineer?

Design verification engineers are professionals who ensure that hardware or software designs meet their intended specifications and function correctly before production or release. They develop and execute tests, write verification plans, create simulation environments, and identify design flaws or errors. Their work is critical in industries like semiconductor, electronics, and software development to prevent costly mistakes and ensure high-quality products. Design verification engineers often work closely with design and validation teams throughout the product development lifecycle.

What are the key skills and qualifications needed to thrive as a design verification engineer?

To thrive as a Design Verification Engineer, you need a solid background in digital design, verification methodologies, and programming languages like SystemVerilog, typically supported by a degree in electrical engineering or a related field. Familiarity with verification tools such as UVM, simulation environments, and EDA software is essential, along with knowledge of scripting languages like Python or Perl. Strong analytical thinking, attention to detail, and effective teamwork are standout soft skills in this role. These skills ensure accurate validation of complex hardware designs, reducing errors and supporting reliable product development cycles.

What are some common challenges faced by design verification engineers, and how can they be addressed?

Design Verification engineers often encounter challenges such as managing complex testbenches, debugging intricate corner cases, and ensuring coverage completeness within tight project timelines. To address these, it’s important to have strong scripting skills, collaborate closely with design and validation teams, and make effective use of verification methodologies like UVM. Regular communication and review cycles also help catch issues early and improve overall verification quality.

What is the difference between Design Verification vs Design Validation?

AspectDesign VerificationDesign Validation
PurposeEnsures the design meets specified requirements through testing and analysisConfirms the final product fulfills user needs and intended use
TimingDuring the development phaseAfter the product is developed and before release
MethodsInspections, reviews, testing, analysisUser testing, field trials, real-world testing
FocusDesign correctness and complianceProduct effectiveness and user satisfaction

While Design Verification checks if the design meets specified requirements during development, Design Validation ensures the final product performs effectively in real-world conditions. Both are essential steps in the product development process to deliver a reliable and user-centered product.

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Cities with the most Design Verification job openings:

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Design Verification jobs near you
Infographic showing various Design Verification job openings in the United States as of August 2026, with employment types broken down into 89% Full Time, 7% Part Time, and 4% Contract. Highlights an 83% Physical, 5% Hybrid, and 12% Remote job distribution, with an average salary of $149,150 per year, or $71.7 per hour.

Design Verification Engineer

HCP ONE LLC

San Jose, CA • On-site

$159K - $194K/yr

Other

Posted 15 days ago

Job description

Job Title: Design Verification Engineer
Location: San Jose, CA
Experience: 8+ Years
Type: Contract
Description:
This requirement is for a Senior Design Verification (DV) Engineer focused on verifying complex semiconductor IPs and SoCs before silicon fabrication. The client is looking for someone who can independently build verification environments, create test plans, and identify design bugs early in the development cycle.
 
Key Skills Required
·  8+ years of Design Verification experience in semiconductor/ASIC/SoC development.
·  Strong expertise in System Verilog.
·  Extensive experience with UVM (Universal Verification Methodology).
·  Experience verifying IP blocks and SoC-level designs.
·  Strong debugging and functional verification skills.
·  Scripting experience in Python, Perl, or Shell.
·  Ability to collaborate with RTL designers and architects to resolve design issues.
Experience writing:
o   Testbenches
o   Testcases
o   Assertions (SVA)
o   Functional coverage
 
Roles & Responsibilities:
·  Develop and maintain UVM-based verification environments.
·  Create verification plans based on design specifications.
·  Write System Verilog testbenches and assertions.
·  Execute simulations and analyze failures.
·  Debug RTL and verification issues.
·  Measure functional coverage and ensure verification closure.
·  Automate regression runs using scripting languages.
·  Work closely with design and architecture teams throughout the development cycle.
 
Must-Have Skills:
·  8+ years Design Verification
·  System Verilog
·  UVM
·  IP/SoC Verification
·  Functional Verification
·  Assertions (SVA)
·  Python/Perl/Shell scripting
·  Debugging RTL issues

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