ZipRecruiter

Log In

1

Design Verification Jobs (NOW HIRING)

Intel

Design Verification Engineer

Santa Clara, CA · On-site

$141K - $200K/yr

Intel is seeking a Design Verification Engineer for the Silicon Chassis team. In this role, you will contribute to verification of next-generation interconnect and chassis IPs that scale across ...

Apple

Design Verification Engineer

Austin, TX

$175K - $308K/yr

Description As a Design Verification Engineer, you'll be at the center of our silicon design group's verification efforts, ensuring the quality and reliability of next-generation cellular systems.

Lorven Technologies

Design verification Engineer

San Jose, CA · On-site

$158K - $192K/yr

Design Verification Engineer Location: San Jose, CA We are seeking DV engineers to verify complex internal IP blocks such as compute engines, accelerators, and custom logic within SoC environments.

Conductor

Director, Design Verification

San Jose, CA · On-site

$219K - $351K/yr

Director, Design Verification - Samsung Semiconductor TheDRAM Development Lab (DDL) within Samsung's Memory Business Unit is focused on cutting‑edge memory and storage solutions for cloud and data ...

Quest Global

Design Verification Engineer

Santa Clara, CA · Remote

$160K - $180K/yr

Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage * Debug, root-cause and resolve functional failures in the design, partnering ...

Texas Instruments

Design Verification Engineer

Dallas, TX · On-site

$123K - $151K/yr

As a Design Verification Engineer, you will work across the full verification cycle - from understanding the system/design intent, developing detailed verification plans and building test benches ...

Apple

Design Verification Lead

Austin, TX · On-site

$134K - $164K/yr

We are seeking a Senior Engineering Leader - in the area of Silicon Design Verification to lead one or more high-caliber verification teams in developing cutting-edge silicon IPs. In this role, you ...

Texas Instruments

Design Verification Engineer

Dallas, TX · On-site

$123K - $151K/yr

As a Design Verification Engineer, you will work across the full verification cycle - from understanding the system/design intent, developing detailed verification plans and building test benches ...

Apple

Design Verification Lead

Austin, TX · On-site

$134K - $164K/yr

We are seeking a Senior Engineering Leader - in the area of Silicon Design Verification to lead one or more high-caliber verification teams in developing cutting-edge silicon IPs. In this role, you ...

TylSemi

Design Verification Architect

San Jose, CA · On-site

$159K - $194K/yr

We are seeking a highly experienced Design Verification Architect to lead the definition and execution of scalable, reusable, and high-quality verification strategies for next-generation SoCs ...

Optimalsemi

Design Verification Engineer

Dallas, TX · On-site

$135K - $164K/yr

Fiori Technology Solutions is currently hiring for a Design Verification Engineer. This is fulltime permanent position. We are looking to fill multiple Design Verification openings. We are ...

Baidu USA

Design Verification Engineer

Sunnyvale, CA · On-site

$159K - $194K/yr

Description We are looking for an experienced design verification engineer to join our SoC team at Baidu's Sunnyvale office. The successful candidate will be a motivated self-starter who will thrive ...

iFlow Inc

Design Verification Engineer

Santa Clara, CA · On-site

$159K - $195K/yr

Design Verification Engineer Location:Santa Clara CA Duration: Long term Experience:8-15 Years Description : Key Responsibilities: Strong understanding of SV and UVM and good debugging skills.

Apple Inc.

Design Verification Lead

Austin, TX · On-site

$134K - $164K/yr

We are seeking a Senior Engineering Leader - in the area of Silicon Design Verification to lead one or more high‑caliber verification teams in developing cutting‑edge silicon IPs. In this role ...

Redolent, Inc.

Design Verification Engineer

Santa Clara, CA · On-site

$159K - $195K/yr

We are seeking a skilled Design Verification Engineer to join our hardware engineering team. The ideal candidate will be responsible for verifying complex digital designs using advanced verification ...

Correct Designs

Design Verification Engineer

Austin, TX · On-site

$134K - $164K/yr

Design Verification Engineer Looking for new challenges? Would you like the variety of a contract position along with long term stability and benefits? Correct Designs can give it all to you. Correct ...

INA Solution Inc

Design verification engineer

San Diego, CA · Remote

$139K - $169K/yr

Design Verification Engineer Location: Remote anywhere in the USA and Canada Duration: Full-time (REMOTE) VISA: ONLY USC AND GC We are looking for humble geniuses, who believe that engineering has ...

previous page

Showing results 41-60

All JobsTechnology JobsSoftware JobsSoftware Quality Engineer JobsDesign Verification Jobs

Design Verification information

See salary details

$105.5K

$149.2K

$167K

How much do design verification jobs pay per year?

As of Sep 10, 2026, the average yearly pay for design verification in the United States is $149,150.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $166,000.00 per year, depending on experience, location, and employer.

What is a design verification engineer?

Design verification engineers are professionals who ensure that hardware or software designs meet their intended specifications and function correctly before production or release. They develop and execute tests, write verification plans, create simulation environments, and identify design flaws or errors. Their work is critical in industries like semiconductor, electronics, and software development to prevent costly mistakes and ensure high-quality products. Design verification engineers often work closely with design and validation teams throughout the product development lifecycle.

What are the key skills and qualifications needed to thrive as a design verification engineer?

To thrive as a Design Verification Engineer, you need a solid background in digital design, verification methodologies, and programming languages like SystemVerilog, typically supported by a degree in electrical engineering or a related field. Familiarity with verification tools such as UVM, simulation environments, and EDA software is essential, along with knowledge of scripting languages like Python or Perl. Strong analytical thinking, attention to detail, and effective teamwork are standout soft skills in this role. These skills ensure accurate validation of complex hardware designs, reducing errors and supporting reliable product development cycles.

What are some common challenges faced by design verification engineers, and how can they be addressed?

Design Verification engineers often encounter challenges such as managing complex testbenches, debugging intricate corner cases, and ensuring coverage completeness within tight project timelines. To address these, it’s important to have strong scripting skills, collaborate closely with design and validation teams, and make effective use of verification methodologies like UVM. Regular communication and review cycles also help catch issues early and improve overall verification quality.

What is the difference between Design Verification vs Design Validation?

AspectDesign VerificationDesign Validation
PurposeEnsures the design meets specified requirements through testing and analysisConfirms the final product fulfills user needs and intended use
TimingDuring the development phaseAfter the product is developed and before release
MethodsInspections, reviews, testing, analysisUser testing, field trials, real-world testing
FocusDesign correctness and complianceProduct effectiveness and user satisfaction

While Design Verification checks if the design meets specified requirements during development, Design Validation ensures the final product performs effectively in real-world conditions. Both are essential steps in the product development process to deliver a reliable and user-centered product.

More about Design Verification jobs

What cities are hiring for Design Verification jobs?

Cities with the most Design Verification job openings:

What are the most commonly searched types of Design Verification jobs?

The most popular types of Design Verification jobs are:

What states have the most Design Verification jobs?

States with the most job openings for Design Verification jobs include:

What job categories do people searching Design Verification jobs look for?

The top searched job categories for Design Verification jobs are:

What other helpful pages are available for Design Verification?

Other pages related to Design Verification:

Design Verification jobs near you
Infographic showing various Design Verification job openings in the United States as of September 2026, with employment types broken down into 50% Internship, and 50% Full Time. Highlights an 100% In-person job distribution, with an average salary of $149,150 per year, or $71.7 per hour.

Design Verification Engineer

Santa Clara, CA • On-site

Intel
Manufacturing • 10K+ employees
Learn more about Intelexternal

$141K - $200K/yr

Full-time

Medical, Retirement, PTO

Re-posted 23 days ago

Intel rating

8.7

Company rating: 8.7 out of 10

Based on 147 frontline employees who took The Breakroom Quiz

Job description

Job Details:Job Description: 

Intel is seeking a Design Verification Engineer for the Silicon Chassis team. In this role, you will contribute to verification of next-generation interconnect and chassis IPs that scale across multiple product families. You will work closely with senior engineers to build and execute robust verification plans, develop high-quality reusable environments, and help deliver first-pass silicon success through strong design verification practices. This role requires strong programming and algorithmic problem-solving skills, hands-on verification development, and willingness to work across traditional discipline boundaries. AI-assisted workflows are part of everyday development here.

Responsibilities
- Develop and execute verification plans and testbenches for interconnect and chassis IP/features at IP and subsystem level
- Build reusable verification components, checkers, constrained-random tests, and debug infrastructure to improve coverage and productivity
- Work with architecture, design, and software teams on spec reviews, feature clarification, bug triage, and closure; contribute outside strict DV boundaries when needed
- Analyze simulation failures, root-cause issues quickly, and drive fixes to closure with clear technical communication
- Contribute to functional coverage planning, coverage closure, and quality signoff under guidance of technical leads
- Contribute to both simulation and formal verification efforts; continuously improve verification automation, regression quality, and development efficiency

You should also demonstrate: Proven ability to write clean, reusable, and maintainable verification code and automation scripts, and to collaborate effectively across architecture, design, and software teams

Qualifications:

Minimum Qualifications
- BS/MS in Electrical Engineering, Computer Science, or related field, with 3+ years of relevant experience in design verification
- Programming fundamentals and algorithmic problem-solving skills, with demonstrated hands-on coding experience in SystemVerilog, C/C++, and Python
- Foundation in simulation-based verification methodologies UVM/ABV, with exposure to formal verification concepts; testbench development, debugging, and coverage-driven verification
- Hands-on experience using AI-assisted development tools as part of daily workflow for coding, debugging, and test development

Preferred Qualifications
- Exposure to interconnects and bus protocols for example AMBA AXI/ACE/CHI, PCIe, CXL, UCIe
- Understanding of cache coherency and memory consistency models
- Experience with external interfaces and system integration debug
- Experience with formal verification tools (JasperGold, VC Formal, or similar) and emulation or FPGA-based verification
- Exposure to RTL concepts, physical design, or CAD tool flows
- Prior work with system IPs such as MMUs SMMU or IOMMU and interrupt controllers

Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, California, Santa ClaraAdditional Locations:Business group:The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $141,910.00-200,340.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

What Intel employees say

Pay

Benefits

Hours and flexibility

Workplace

Get the full story on Breakroom

Intel logo

About Intel

Sourced by ZipRecruiter

Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth

Industry

Manufacturing

Company size

10,000+ Employees

Headquarters location

Santa Clara, CA, US

Year founded

1968

View All Intel Jobs

Apply