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Design Verification Jobs (NOW HIRING)

SOC Design Verification Engineer

Dallas, TX · On-site

$127K - $156K/yr

SOC Design Verification Engineer Location: Redmond, WA (Onsite) Duration: 10 Months Minimum Qualifications • Track record of 'first-pass success' in ASIC development cycles. • Bachelor's degree ...

As a Design Verification Engineer, you will be part of an agile team working with experienced engineers across the industry, focused on developing ASIC solutions for Meta's data center applications.

Design Verification Engineer

Plano, TX · On-site

$130K - $158K/yr

and other details - We are seeking an ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define ...

ASIC Design Verification Engineer

$139K - $169K/yr

Drive Design Verification to closure using defined verification metrics for test plans, functional coverage, and code coverage. * Debug, root-cause, and resolve functional failures in the design in ...

As a Design Verification Engineer, you will be part of an agile team working with experienced engineers across the industry, focused on developing ASIC solutions for Meta's data center applications.

Design Verification Engineer

Irvine, CA

$146K - $178K/yr

Design Verification Engineer Location: Santa Clara, CA Duration: 06 months (High Possibility of an extension) Senior DV engineer responsible for defining and implementing verification methodology and ...

Design Verification Engineer

Beaverton, OR · On-site

$141K - $172K/yr

Design Verification Engineers at Apple are responsible for verifying the functionality and performance of Apple's premier SOCs. This is a critical job within Apple's Hardware Technology and we'd love ...

Design Verification Architect

San Jose, CA · On-site

$150K - $300K/yr

Role Overview We are seeking a highly experienced Design Verification Architect to lead the definition and execution of scalable, reusable, and high-quality verification strategies for next ...

As a Design Verification Engineer, you will be part of a team working with experienced engineers across the industry, focused on developing advanced ASIC solutions for Meta's data center applications.

As a Design Verification Engineer, you will be part of a team working with experienced engineers across the industry, focused on developing advanced ASIC solutions for Meta's data center applications.

Design Verification Lead

Cupertino, CA · On-site

$167K - $204K/yr

We are looking for a remarkable Design Verification Lead to work with multi-functional teams and external vendors to define, develop and productize the next generation of mobile solutions.

Design Verification Engineer

Irvine, CA · On-site

$146K - $178K/yr

Design Verification Engineer Location: Santa Clara, CA Duration: 06 months (High Possibility of an extension) Senior DV engineer responsible for defining and implementing verification methodology and ...

Design Verification Engineer

Cupertino, CA · On-site

$167K - $204K/yr

Design Verification Engineers at Apple are responsible for verifying the functionality and performance of Apple's premier SOCs. This is a critical job within Apple's Hardware Technology and we'd love ...

Senior Design Verification Engineer

San Diego, CA · On-site

$144K - $176K/yr

Design Verification Engineer Duration: Full time or Contract Location: Bay Area, CA About Us: We are representing Sivaltech, A design services company headquartered in Milpitas, CA. We provide ...

As a Design Verification Engineer at Lightmatter, you will find yourself at the heart of a dynamic, interdisciplinary team. Your role will involve close collaboration with our digital design experts ...

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Showing results 1-20

Design Verification information

See salary details

$105.5K

$149.2K

$167K

How much do design verification jobs pay per year?

As of Jul 9, 2026, the average yearly pay for design verification in the United States is $149,150.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $166,000.00 per year, depending on experience, location, and employer.

What is the difference between Design Verification vs Design Validation?

AspectDesign VerificationDesign Validation
PurposeEnsures the design meets specified requirements through testing and analysisConfirms the final product fulfills user needs and intended use
TimingDuring the development phaseAfter the product is developed and before release
MethodsInspections, reviews, testing, analysisUser testing, field trials, real-world testing
FocusDesign correctness and complianceProduct effectiveness and user satisfaction

While Design Verification checks if the design meets specified requirements during development, Design Validation ensures the final product performs effectively in real-world conditions. Both are essential steps in the product development process to deliver a reliable and user-centered product.

What are design verification engineers?

Design verification engineers are professionals who ensure that hardware or software designs meet their intended specifications and function correctly before production or release. They develop and execute tests, write verification plans, create simulation environments, and identify design flaws or errors. Their work is critical in industries like semiconductor, electronics, and software development to prevent costly mistakes and ensure high-quality products. Design verification engineers often work closely with design and validation teams throughout the product development lifecycle.

What are the key skills and qualifications needed to thrive as a Design Verification Engineer, and why are they important?

To thrive as a Design Verification Engineer, you need a solid background in digital design, verification methodologies, and programming languages like SystemVerilog, typically supported by a degree in electrical engineering or a related field. Familiarity with verification tools such as UVM, simulation environments, and EDA software is essential, along with knowledge of scripting languages like Python or Perl. Strong analytical thinking, attention to detail, and effective teamwork are standout soft skills in this role. These skills ensure accurate validation of complex hardware designs, reducing errors and supporting reliable product development cycles.

What are some common challenges faced by Design Verification engineers, and how can they be addressed?

Design Verification engineers often encounter challenges such as managing complex testbenches, debugging intricate corner cases, and ensuring coverage completeness within tight project timelines. To address these, it’s important to have strong scripting skills, collaborate closely with design and validation teams, and make effective use of verification methodologies like UVM. Regular communication and review cycles also help catch issues early and improve overall verification quality.
More about Design Verification jobs
What cities are hiring for Design Verification jobs? Cities with the most Design Verification job openings:
What are the most commonly searched types of Design Verification jobs? The most popular types of Design Verification jobs are:
What states have the most Design Verification jobs? States with the most job openings for Design Verification jobs include:
Infographic showing various Design Verification job openings in the United States as of July 2026, with employment types broken down into 89% Full Time, 8% Part Time, and 3% Contract. Highlights an 87% Physical, 3% Hybrid, and 10% Remote job distribution, with an average salary of $149,150 per year, or $71.7 per hour.

Design Verification Engineer

Mirafra Technology

San Diego, CA

$144K - $176K/yr

Full-time

Re-posted 27 days ago


Job description

Company Description

Mirafra is a global product engineering services company with expertise in semiconductor design, embedded and application software.

Job Description

Job Title : Design Verification Engineer

Job Type : Full time

Location : San Diego And Bay Area

Job Description :
Strong verification skills: test planning, problem solving, debug,
adversarial testing. Multimedia Camera Image processing, Video or graphics
hardware experience is preferred.
Strong working knowledge of HVLs: System Verilog, VERA/e-Specman, System C.
Experience with methodologies like RVM/VMM/OVM/UVM. RTL design experience
and/or very strong OOPs programming experience is also a plus.
Good written and oral communications skills required.
Experience with simulation acceleration tool like Veloce/Palladium is a plus.
Skill required:
CPU, (MC: middle core, ARM architecture)
Decent knowledge of assertions.
SV and decent UVM knowledge
Code coverage.
Verilog or VHDL, C/C++, Tcl/Perl/shell-scripting.

Additional Information

All your information will be kept confidential according to EEO guidelines.